first upload

LICENSE

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+COPYRIGHT
+
+All contributions by Brown University (Scale Lab):
+Copyright (c) 2015, 2016, The Regents of Brown University
+All rights reserved.
+
+All other contributions:
+Copyright (c) 2015, 2016, the respective contributors
+All rights reserved.
+
+ABACUS uses a shared copyright model: each contributor holds copyright over
+their contributions to ABACUS. The project versioning records all such
+contribution and copyright details. If a contributor wants to further mark
+their specific copyright on a particular contribution, they should indicate
+their copyright solely in the commit message of the change when it is
+committed.
+
+LICENSE
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met: 
+
+1. Redistributions of source code must retain the above copyright notice, this
+   list of conditions and the following disclaimer. 
+2. Redistributions in binary form must reproduce the above copyright notice,
+   this list of conditions and the following disclaimer in the documentation
+   and/or other materials provided with the distribution. 
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+CONTRIBUTION AGREEMENT
+
+By contributing to the ABACUS repository through pull-request, comment,
+or otherwise, the contributor releases their content to the
+license and copyright terms herein.

blockmatching/Original/me_PE.v

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+`timescale 1ns / 1ps
+module me_PE(clk, A, B, AD);
+
+	input clk;
+	input [7:0] A,B;
+	output reg[7:0] AD;
+
+	wire A_smaller;
+	wire [7:0] D, E;
+
+	assign A_smaller = (A < B);
+	assign D = A_smaller ? B : A;
+	assign E = A_smaller ? A : B;
+
+	always @ (posedge clk)
+	begin
+		AD <= D - E;
+	end
+
+endmodule

blockmatching/Original/me_bram_search_2column.v

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+`timescale 1ns/1ps
+module me_bram_search_2column(  //INPUTS
+                    clk, 
+                    search_read_addr, 
+                    search_write_addr, 
+                    search_write_data, 
+					search_read, 
+                    search_write, 
+                    //OUTPUT
+                    search_data_out);
+
+input clk;
+input [6:0] search_read_addr;
+input [6:0] search_write_addr;
+input [7:0] search_write_data;
+input search_read, search_write;
+
+output [7:0] search_data_out;
+
+reg [6:0] search_read_addr_d;
+
+reg [7:0] reg_file[0:93];
+
+assign search_data_out = reg_file[search_read_addr_d];
+
+always @(posedge clk)
+begin
+   if (search_read) search_read_addr_d <= search_read_addr;
+   if (search_write) reg_file[search_write_addr] <= search_write_data;
+end
+
+endmodule

blockmatching/Original/me_bram_search_3column.v

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+`timescale 1ns/1ps
+module me_bram_search_3column(  //INPUTS
+                    clk, 
+                    search_read_addr, 
+                    search_write_addr, 
+                    search_write_data, 
+                    search_read, 
+                    search_write, 
+                    //OUTPUT
+                    search_data_out);
+
+input clk;
+input [7:0] search_read_addr;
+input [7:0] search_write_addr;
+input [7:0] search_write_data;
+input search_read, search_write;
+
+output [7:0] search_data_out;
+
+reg [7:0] search_read_addr_d;
+
+reg [7:0] reg_file[0:140];
+
+assign search_data_out = reg_file[search_read_addr_d];
+
+always @(posedge clk)
+begin
+   if (search_read) search_read_addr_d <= search_read_addr;
+   if (search_write) reg_file[search_write_addr] <= search_write_data;
+end
+
+endmodule

blockmatching/Original/me_comparator.v

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+`timescale 1ns/1ps
+module me_comparator (clk, reset, clear, start16, position16, inSAD41, finalSAD41, positionSAD41);
+
+	input clk;
+	input reset, clear;
+	input start16;
+
+	input [9:0] position16;
+
+	input [15:0] inSAD41;
+
+	output reg [15:0] finalSAD41;
+
+	output reg [9:0] positionSAD41;
+
+	always @ (posedge clk or posedge reset)
+	begin
+	if (reset)
+	begin
+		positionSAD41  <= 10'd0;
+	//
+		finalSAD41  <= 16'hFFFF;
+	end
+	else if (clear)
+	begin
+		positionSAD41  <= 10'd0;
+//
+		finalSAD41  <= 16'hFFFF;
+    end	
+	else 
+	begin
+		if (start16 == 1'b1)
+		begin
+			if (inSAD41 < finalSAD41)
+				begin
+					finalSAD41 <= inSAD41;
+					positionSAD41 <= position16;
+				end
+			else
+				begin
+					finalSAD41 <= finalSAD41;
+					positionSAD41 <= positionSAD41;
+				end
+			end
+		end
+	end
+endmodule