how to generate bitstream file by myself ?

[gobs-code]

Hi Sergey,

At first，thanks for your source code about risc-v cores.

I know I can directly use your project at ISE or Vivado(riscv_vhdl/rocket_soc/prj/) but I want to synthesis in vivado by myself at xilinx VCU118 Board. Can you tell me which vhdl files need to add my project and other attention items?

Thanks you very much !

[sergeykhbr]

Hi,
I'm doing the following steps to add new fpga/asic target:

1. Create new target ID in the file techmap/gencomp/gecomp.vhd (or reuse 'virtex7' for your purpose).
2. Generate new PLL module for your target and add it to the file techmap/pll/SysPLL_tech.vhd under your generic parameter. Don't forget to include your pll module into 'techmap' library (default is 'work').
3. Do the same step for others '_*tech.vhd' files (if needed), like techmap/mem/bootrom_tech.vhd or check that function is_fpga('virtex7') returns 1.
4. Create the constrains file for your fpga
5. Create the target config file (analog is prj/ml605/config_v6.vhd) and include it into the project instead of other config target. It should define parameters:
   CFG_FABTECH = virtex7
   CFG_MEMTECH = virtex7
   ..
6. Build project and try to find the words 'blackbox' or 'black' in your synthesis output. If not found then OK and everything should be built successfully, otherwise check that you properly included target dependable modules.

[gobs-code]

@sergeykhbr Hi sergey，
Thanks for your reply ,I want to ask one question that adding helloworld hex file to vhdl file synthesis together which attention items we need focus on and why print "hello world !" message by uart port is messy code.

please give me some hint,thanks again!

[sergeykhbr]

There're used two images:

1. bootimage.hex. This file is generated by fw/boot code. It is valid for ASIC, FPGA and RTL simulation. But there's implemented a special trick (reading 'tech' register from pnp module) for the RTL simulation that allows to skip stage of copying fwimage data from ROM to RAM before executing it.

2. fwimage.hex. It's the image with the firmware (HelloWorld or whatever). In normal mode it should be stored only as a ROM module but to speed simulation SRAM module also is using it for the initialization. This approach normally works on simulation and even for FPGA but invalid for ASIC because SRAM cannot be initialized.

If you have some messy UART output most probably you wrongly setup UART Baud rate. Baud Rate directly depends of Bus clock frequency and UART scaler register must be computed as:

    uart->scaler = Fbus / 115200 / 2
    where Fbus = 40 000 000 Hz

Probably you are using another Bus Frequency.

[gobs-code]

@sergeykhbr Hi sergey,
Thanks for you patient, I'm very appreciate it !

[gobs-code]

@sergeykhbr Hi sergey，
I'm sorry , I can't generate bitstream file for my target board (Virtex UltraScala+ VCU118) following your hints. Can you tell me every steps transplant RISC-V core to my board or create new project in vivado(or ISE) for my board. My board XDC file following:
riscv_soc_vcu118.txt

[sergeykhbr]

Sorry, I was on vacation.
Where did you stuck? Could you please send synthesis console logs. Because I don't have such board and can't check your constraints file.

[gobs-code]

@sergeykhbr Thank you for your patient!

Vivado synthesis has passed, but implementation report errors , the error is follow:

[DRC 23-20] Rule violation (INBB-3) Black Box Instances - Cell 'boot0/tech0/genrom1.x0' of type 'boot0/tech0/genrom1.x0/BootRom_vcu118' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully.

my vivado synthesis log:
vivado_synthesis_log.txt

my vivado implementation log:
vivado_implementation_log.txt

[sergeykhbr]

I see at least 2 wrongly synthesized component (see synt. log-file):

Report BlackBoxes: 
     +------+----------------+----------+
     |      |BlackBox name   |Instances |
     +------+----------------+----------+
     |1     |BootRom_vcu118  |         1|
     |2     |RomImage_vcu118 |         1|
     +------+----------------+----------+

So you need to properly instantiate these modules in a similar way as in techmap\mem\bootrom_tech.vhd

1. Check is_fpga(memtech) returns true
2. Check that your files included into techmap library
3. There's a bit another names than in my project so I can't provide more details.

[gobs-code]

Thanks for your patient, My modification steps as follow:

1.create BootRom_vcu118.vhd for my target.
2.instantiation the modules in techmap\mem\bootrom.vhd
( RomImage_vcu118.vhd also like above )
So,besides I don't know which file need to modification .Can you tell all of *.vhd file need to modification about BootRom and RomImage.

[sergeykhbr]

If you create new ROM-module file then you need to add it into Vivado project and afterward you need to include it into 'techmap' library (default is 'work').

Now it looks like you didn't add your files into the project or didn't include them into proper library by this reason Vivado insert black-boxes.

[gobs-code]

Okay,Thanks you very much!!!