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I desiged Chisel and RISC-V Based Single Cycle Core
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I designed Chisel and RISC-V Based Five Stage Pipeline Core
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I worked on python basec Burq simulator to verify the Chisel and Verilog based cores
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I worked on scala based projects using functional programming
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I’m currently working to automate Berkeley Analog Generator using Reinforcement Learning and also Chisel based projects
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How to reach me siddiquimohsin660@gmail.com
