hypervisor: arm64: add linux inmate cell config for foundation-v8

Add the cell configuration files, and some helper scripts and device
tree for the foundation-v8 model. These can be used to load a linux
inmate on a cell on that target.

Signed-off-by: Dmitry Voytik <dmitry.voytik@huawei.com>
Signed-off-by: Antonios Motakis <antonios.motakis@huawei.com>
[antonios.motakis@huawei.com: split off as a separate patch,
	some minor renaming for consistency]

configs/foundation-v8-linux-demo.c

@@ -0,0 +1,72 @@
+/*
+ * Jailhouse AArch64 support
+ *
+ * Copyright (C) 2015 Huawei Technologies Duesseldorf GmbH
+ *
+ * Authors:
+ *  Dmitry Voytik <dmitry.voytik@huawei.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2.  See
+ * the COPYING file in the top-level directory.
+ */
+
+#include <linux/types.h>
+#include <jailhouse/cell-config.h>
+
+#define ARRAY_SIZE(a) sizeof(a) / sizeof(a[0])
+
+struct {
+	struct jailhouse_cell_desc cell;
+	__u64 cpus[1];
+	struct jailhouse_memory mem_regions[2];
+	struct jailhouse_irqchip irqchips[1];
+} __attribute__((packed)) config = {
+	.cell = {
+		.signature = JAILHOUSE_CELL_DESC_SIGNATURE,
+		.name = "linux-inmate-demo",
+		.flags = JAILHOUSE_CELL_PASSIVE_COMMREG,
+
+		.cpu_set_size = sizeof(config.cpus),
+		.num_memory_regions = ARRAY_SIZE(config.mem_regions),
+		.num_irqchips = 1,
+		.pio_bitmap_size = 0,
+		.num_pci_devices = 0,
+	},
+
+	.cpus = {
+		0xc, /* 2nd and 3rd CPUs */
+	},
+
+	/* Physical memory map:
+	 * 0x0_0000_0000 - 0x0_7fff_ffff (2048 MiB) Devices
+	 * 0x0_8000_0000 - 0x0_bbdf_ffff ( 958 MiB) Ram, root cell Kernel
+	 * 0x0_bbe0_0000 - 0x0_fbff_ffff (1026 MiB) Ram, nothing
+	 * 0x0_fc00_0000 - 0x1_0000_0000 (  64 MiB) Ram, hypervisor
+	 * ...                           (  30 GiB)
+	 * 0x8_8000_0000 - 0x9_0000_0000 (2048 MiB) Ram, nonroot cells
+	 */
+	.mem_regions = {
+		/* uart3 */ {
+			.phys_start = 0x1c0c0000,
+			.virt_start = 0x1c090000,	/* inmate lib uses */
+			.size = 0x1000,
+			.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+				JAILHOUSE_MEM_IO,
+		},
+		/* RAM load */ {
+			.phys_start = 0x880000000,
+			.virt_start = 0x0,
+			.size = 0x10000000,	/* 256 MiB */
+			.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+				JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE,
+		},
+	},
+
+	.irqchips = {
+		/* GIC */ {
+			/* address should be the same as in root cell */
+			.address = 0x2c001000,
+			.pin_bitmap = (1 << 8), /* uart3 */
+		},
+	}
+};

samples/kernel-inmate-foundation-v8.dts

@@ -0,0 +1,103 @@
+/*
+ * Jailhouse AArch64 support
+ *
+ * Copyright (C) 2015 Huawei Technologies Duesseldorf GmbH
+ *
+ * Authors:
+ *  Dmitry Voytik <dmitry.voytik@huawei.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2.  See
+ * the COPYING file in the top-level directory.
+ *
+ * ARMv8 Foundation model DTS
+ *
+ */
+
+/dts-v1/;
+
+/* 64 KiB */
+/memreserve/ 0x0 0x00010000;
+
+/ {
+	model = "Jailhouse-Foundation-v8A";
+	compatible = "arm,foundation-aarch64", "arm,vexpress";
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+		bootargs = "earlycon";
+	};
+
+	aliases {
+		serial0 = &serial0;
+	};
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		cpu@2 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x2>;
+			enable-method = "psci";
+			next-level-cache = <&L2_0>;
+		};
+
+		cpu@3 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x3>;
+			enable-method = "psci";
+			next-level-cache = <&L2_0>;
+		};
+
+		L2_0: l2-cache0 {
+			compatible = "cache";
+		};
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x10000000>;	/* 256 MiB starts at 0x0 */
+	};
+
+	gic: interrupt-controller@2c001000 {
+		compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
+		#interrupt-cells = <3>;
+		#address-cells = <0>;
+		interrupt-controller;
+		reg = <0x0 0x2c001000 0 0x1000>,
+		      <0x0 0x2c002000 0 0x1000>;
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <1 13 0xf08>,
+			     <1 14 0xf08>,
+			     <1 11 0xf08>;
+		clock-frequency = <100000000>;
+	};
+
+	v2m_clk24mhz: clk24mhz {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <24000000>;
+		clock-output-names = "v2m:clk24mhz";
+	};
+
+	serial0: uart@1c090000 {
+		compatible = "arm,pl011", "arm,primecell";
+		reg = <0x0 0x1c090000 0x0 0x1000>;
+		interrupts = <0 8 1>;
+		clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
+		clock-names = "uartclk", "apb_pclk";
+	};
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+};