core: ivshmem: Move INTx control into PCI config space

This prepares for unprivileged access to the MMIO register space inside
cells. It uses the flags field of the new vendor capability.

To avoid affecting the arch_ivshmem_update_intx handler from further
changes in the enabling logic, pass the new state as parameter.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>

hypervisor/arch/arm-common/ivshmem.c

@@ -41,14 +41,14 @@ int arch_ivshmem_update_msix(struct pci_device *device)
 	return 0;
 }
 
-void arch_ivshmem_update_intx(struct ivshmem_endpoint *ive)
+void arch_ivshmem_update_intx(struct ivshmem_endpoint *ive, bool enabled)
 {
 	u8 pin = ive->cspace[PCI_CFG_INT/4] >> 8;
 	struct pci_device *device = ive->device;
 
 	if (device->info->num_msix_vectors != 0)
 		return;
 
-	ive->arch.irq_id = (ive->intx_ctrl_reg & IVSHMEM_INTX_ENABLE) ?
+	ive->arch.irq_id = enabled ?
 		(32 + device->cell->config->vpci_irq_base + pin - 1) : 0;
 }

hypervisor/arch/x86/ivshmem.c

@@ -65,6 +65,6 @@ int arch_ivshmem_update_msix(struct pci_device *device)
 	return 0;
 }
 
-void arch_ivshmem_update_intx(struct ivshmem_endpoint *ive)
+void arch_ivshmem_update_intx(struct ivshmem_endpoint *ive, bool enabled)
 {
 }

hypervisor/include/jailhouse/ivshmem.h

@@ -20,8 +20,6 @@
 
 #define IVSHMEM_CFG_SIZE	0x60
 
-#define IVSHMEM_INTX_ENABLE	0x1
-
 /**
  * @defgroup IVSHMEM ivshmem
  * @{
@@ -38,7 +36,6 @@ struct ivshmem_endpoint {
 	struct ivshmem_endpoint *remote;
 	spinlock_t remote_lock;
 	struct arch_pci_ivshmem arch;
-	u32 intx_ctrl_reg;
 };
 
 int ivshmem_init(struct cell *cell, struct pci_device *device);
@@ -69,8 +66,9 @@ int arch_ivshmem_update_msix(struct pci_device *device);
 /**
  * Update cached INTx state (if any) of the given ivshmem device.
  * @param ive		Ivshmem endpoint to be updated.
+ * @param enable	True if INTx is enabled.
  */
-void arch_ivshmem_update_intx(struct ivshmem_endpoint *ive);
+void arch_ivshmem_update_intx(struct ivshmem_endpoint *ive, bool enabled);
 
 /** @} IVSHMEM */
 #endif /* !_JAILHOUSE_IVSHMEM_H */

hypervisor/ivshmem.c

@@ -43,9 +43,11 @@
 #define IVSHMEM_CFG_SHMEM_SIZE	(IVSHMEM_CFG_VENDOR_CAP + 12)
 #define IVSHMEM_CFG_VENDOR_LEN	20
 
+/* Flags in IVSHMEM_CFG_VENDOR_CAP + 3 */
+#define IVHSMEM_CFGFLAG_INTX	(1 << (0 + 24))
+
 #define IVSHMEM_MSIX_VECTORS	1
 
-#define IVSHMEM_REG_INTX_CTRL	0
 #define IVSHMEM_REG_IVPOS	8
 #define IVSHMEM_REG_DBELL	12
 #define IVSHMEM_REG_LSTATE	16
@@ -97,16 +99,6 @@ static enum mmio_result ivshmem_register_mmio(void *arg,
 {
 	struct ivshmem_endpoint *ive = arg;
 
-	if (mmio->address == IVSHMEM_REG_INTX_CTRL) {
-		if (mmio->is_write) {
-			ive->intx_ctrl_reg = mmio->value & IVSHMEM_INTX_ENABLE;
-			arch_ivshmem_update_intx(ive);
-		} else {
-			mmio->value = ive->intx_ctrl_reg;
-		}
-		return MMIO_HANDLED;
-	}
-
 	/* read-only IVPosition */
 	if (mmio->address == IVSHMEM_REG_IVPOS && !mmio->is_write) {
 		mmio->value = ive->ivpos;
@@ -287,7 +279,15 @@ enum pci_access ivshmem_pci_cfg_write(struct pci_device *device,
 	case IVSHMEM_CFG_MSIX_CAP / 4:
 		if (ivshmem_write_msix_control(ive, value))
 			return PCI_ACCESS_REJECT;
+		break;
+	case IVSHMEM_CFG_VENDOR_CAP / 4:
+		ive->cspace[IVSHMEM_CFG_VENDOR_CAP/4] &= ~IVHSMEM_CFGFLAG_INTX;
+		ive->cspace[IVSHMEM_CFG_VENDOR_CAP/4] |=
+			value & IVHSMEM_CFGFLAG_INTX;
+		arch_ivshmem_update_intx(ive, value & IVHSMEM_CFGFLAG_INTX);
+		break;
 	}
+
 	return PCI_ACCESS_DONE;
 }