arm: hide TLB flush behind a macro

Hide TLB flushes issues by the MMU code behind a macro, so we can
increase our chances of reusing some of this code.

Signed-off-by: Antonios Motakis <antonios.motakis@huawei.com>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>

hypervisor/arch/arm/include/asm/processor.h

@@ -197,6 +197,8 @@ static inline bool is_el2(void)
 	return (psr & PSR_MODE_MASK) == PSR_HYP_MODE;
 }
 
+#define tlb_flush_guest()	arm_write_sysreg(TLBIALL, 1)
+
 #endif /* !__ASSEMBLY__ */
 
 #endif /* !_JAILHOUSE_ASM_PROCESSOR_H */

hypervisor/arch/arm/mmu_cell.c

@@ -107,7 +107,7 @@ void arch_cpu_tlb_flush(struct per_cpu *cpu_data)
 	 * Invalidate all stage-1 and 2 TLB entries for the current VMID
 	 * ERET will ensure completion of these ops
 	 */
-	arm_write_sysreg(TLBIALL, 1);
+	tlb_flush_guest();
 	dsb(nsh);
 	cpu_data->flush_vcpu_caches = false;
 }