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core, tools: Introduce cache regions to the cell configuration
Allow to specify regions of caches so that the hypervisor can partition their usage accordingly whenever the hardware supports this. The specification of their start location and sizes depend on the architecture specific partitioning support. So far, only L3 cache types are definable, either as unified cached or further partitioned into code and data (to cater Intel's CAT and CDP). As with memory regions, caches are usually taken from the root cell on non-root cell creation, but they can also be declared as shared with the root cell. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
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