arm, arm64: Fold gic_probe_cpu_id into GICv2 gic_cpu_init

This is the only user, and it is GICv2-only. As a side-effect, this now
actually evaluates the return value.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>

hypervisor/arch/arm-common/gic-common.c

@@ -122,28 +122,6 @@ static enum mmio_result handle_sgir_access(struct mmio_access *mmio)
 	return MMIO_HANDLED;
 }
 
-/*
- * Get the CPU interface ID for this cpu. It can be discovered by reading
- * the banked value of the PPI and IPI TARGET registers
- * Patch 2bb3135 in Linux explains why the probe may need to scans the first 8
- * registers: some early implementation returned 0 for the first ITARGETSR
- * registers.
- * Since those didn't have virtualization extensions, we can safely ignore that
- * case.
- */
-int gic_probe_cpu_id(unsigned int cpu)
-{
-	if (cpu >= ARRAY_SIZE(gicv2_target_cpu_map))
-		return -EINVAL;
-
-	gicv2_target_cpu_map[cpu] = mmio_read32(gicd_base + GICD_ITARGETSR);
-
-	if (gicv2_target_cpu_map[cpu] == 0)
-		return -ENODEV;
-
-	return 0;
-}
-
 void gic_handle_sgir_write(struct sgi *sgi, bool virt_input)
 {
 	struct per_cpu *cpu_data = this_cpu_data();

hypervisor/arch/arm-common/gic-v2.c

@@ -146,8 +146,23 @@ static int gic_cpu_init(struct per_cpu *cpu_data)
 	 */
 	gic_clear_pending_irqs();
 
-	/* Register ourselves into the CPU itf map */
-	gic_probe_cpu_id(cpu_data->cpu_id);
+	/*
+	 * Get the CPU interface ID for this cpu. It can be discovered by
+	 * reading the banked value of the PPI and IPI TARGET registers
+	 * Patch 2bb3135 in Linux explains why the probe may need to scans the
+	 * first 8 registers: some early implementation returned 0 for the first
+	 * ITARGETSR registers.
+	 * Since those didn't have virtualization extensions, we can safely
+	 * ignore that case.
+	 */
+	if (cpu_data->cpu_id >= ARRAY_SIZE(gicv2_target_cpu_map))
+		return -EINVAL;
+
+	gicv2_target_cpu_map[cpu_data->cpu_id] =
+		mmio_read32(gicd_base + GICD_ITARGETSR);
+
+	if (gicv2_target_cpu_map[cpu_data->cpu_id] == 0)
+		return -ENODEV;
 
 	return 0;
 }

hypervisor/arch/arm-common/include/asm/gic.h

@@ -54,7 +54,6 @@ extern u8 gicv2_target_cpu_map[8];
 extern void *gicd_base;
 extern spinlock_t dist_lock;
 
-int gic_probe_cpu_id(unsigned int cpu);
 enum mmio_result gic_handle_dist_access(void *arg, struct mmio_access *mmio);
 enum mmio_result gic_handle_irq_route(struct mmio_access *mmio,
 				      unsigned int irq);