arm: mach-k3: am6_init: Prioritize MSMC traffic over DDR in NAVSS Nor…

…thbridge

NB0 is bridge to SRAM and NB1 is bridge to DDR.

To ensure that SRAM transfers are not stalled due to
delays during DDR refreshes, SRAM traffic should be higher
priority (threadmap=2) than DDR traffic (threadmap=0).

This patch does just that.

This is required to fix ICSSG TX lock-ups due to delays in
MSMC transfers due to incorrect Northbridge configuration.
On SR2 devices, lockups were not observed so far but high retry
rates of ICSSG Ethernet (icssg-eth) and, thus, lower throughput.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Acked-by: Andrew F. Davis <afd@ti.com>
Acked-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: Benoit Parrot <bparrot@ti.com>
[Jan: rebased, dropped used define, extened commit log]
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>

arch/arm/mach-k3/am6_init.c

@@ -151,6 +151,19 @@ int fdtdec_board_setup(const void *fdt_blob)
 	return fixup_usb_boot();
 }
 #endif
+
+static void setup_am654_navss_northbridge(void)
+{
+	/*
+	 * NB0 is bridge to SRAM and NB1 is bridge to DDR.
+	 * To ensure that SRAM transfers are not stalled due to
+	 * delays during DDR refreshes, SRAM traffic should be higher
+	 * priority (threadmap=2) than DDR traffic (threadmap=0).
+	 */
+	writel(0x2, NAVSS0_NBSS_NB0_CFG_BASE + NAVSS_NBSS_THREADMAP);
+	writel(0x0, NAVSS0_NBSS_NB1_CFG_BASE + NAVSS_NBSS_THREADMAP);
+}
+
 void board_init_f(ulong dummy)
 {
 #if defined(CONFIG_K3_LOAD_SYSFW) || defined(CONFIG_K3_AM654_DDRSS)
@@ -168,6 +181,8 @@ void board_init_f(ulong dummy)
 	/* Make all control module registers accessible */
 	ctrl_mmr_unlock();
 
+	setup_am654_navss_northbridge();
+
 #ifdef CONFIG_CPU_V7R
 	disable_linefill_optimization();
 	setup_k3_mpu_regions();

arch/arm/mach-k3/include/mach/am6_hardware.h

@@ -52,4 +52,10 @@
 /* MCU SCRATCHPAD usage */
 #define TI_SRAM_SCRATCH_BOARD_EEPROM_START CONFIG_SYS_K3_MCU_SCRATCHPAD_BASE
 
+/* NAVSS Northbridge config */
+#define	NAVSS0_NBSS_NB0_CFG_BASE			0x03802000
+#define	NAVSS0_NBSS_NB1_CFG_BASE			0x03803000
+
+#define	NAVSS_NBSS_THREADMAP				0x10
+
 #endif /* __ASM_ARCH_AM6_HARDWARE_H */