Add Verilog cell models + UDPs from OpenPDKs

[ubfx]

This patch adds verilog cell models and UDPs unmodified from efabless/skywater-pdk-libs-sky130_fd_sc_hd@89492a0.
The source repository is also under Apache-2.0 license (https://github.com/efabless/skywater-pdk-libs-sky130_fd_sc_hd/blob/master/LICENSE) so an additional license notice should not be necessary.

Fix #15

[ubfx]

Turning this into a draft while I experiment with how to best hand the files over to the simulator. I wanted to avoid merging all the cells into a single Verilog file (like it is also done for the LEFs) to keep the library close to the original. But it seems like keeping them all seperate will just make it more complicated for the simulation steps and also blow up the schema unnecessarily.
By the way, I noticed that the verilog views of the gf180 and asap7 PDKs are not listed in the schema, is there a reason for that? Could we put the Verilog file under the keypath 'output', 'verilog'?

[gadfort]

@ubfx a couple of things:

1. I don't think we need to include the blackbox models (I think that is legacy stuff and all those issues have been resolved to my knowledge).
2. what are the symbol files, those seem to also be blackboxes, and the testbenches? I'm not sure these are needed
3. there are a lot of files, it might be nice to find a way to collapse this into something more manageable. (3000+ files are not that easy to review).
4. They should be added under ('output', 'rtl', 'verilog')

[ubfx]

@gadfort Thank you for the pointers.
I removed all the unnecessary files. However, I think we still need two versions of every cell, the ones with power ports and the ones without. Having two different files and two different keypaths ('rtl', 'verilog' and 'rtlpower', 'verilog') seems a little cumbersome though; so I implemented it by means of a ifdef structure.

[ubfx]

I realized that OpenPDKs already provides a merged version of the model files, using a similar ifdef structure, so I moved over to using theirs instead of using our own merge-script. While the OpenPDK version might be a little worse to read because the license is replicated N times within the file, I think it's still better than adding another slightly different merged version of these files. Also it keeps the names of the Verilog defines (USE_POWER_PINS and FUNCTIONAL) consistent between lambdapdk and OpenPDKs.

[gadfort]

Look good, just needs the commit hash and it should be good to merge

[gadfort]

Looks good. Thank you.