RC2

Close #65 Added DNPed resistors on unused complementary LVPECL outputs - Close #63 Close #61 Close #59 Switched Si549 to CERNlib MMCX net lengths were equalized (xsignals were broken). Additionally some xsignals for differential clocks were broken as well. After fixing some net lengths were adjusted within differential pairs.
sinara-hw · Dec 15, 2019 · 3c3cea0 · 3c3cea0
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diff --git a/ClockRecovery.SchDoc b/ClockRecovery.SchDoc
diff --git a/PCB_3U_Kasli.PrjPCB b/PCB_3U_Kasli.PrjPCB
diff --git a/PCB_3U_Kasli.PrjPCBVariants b/PCB_3U_Kasli.PrjPCBVariants
diff --git a/PCB_Kasli.PCBDOC b/PCB_Kasli.PCBDOC
diff --git a/PcbLib1.PcbLib b/PcbLib1.PcbLib
diff --git a/Schlib1.SchLib b/Schlib1.SchLib