GhostSD

GOST-based SDSC-card encryptor implemented on boards:

• iCESugar-nano
• Tang Primer 20K (with Dock ext-board)
• PYNQ-Z1

SD cards are described in the Physical Layer Simplified Specification by the SD Card Association and the SD Group.

Using the 64-bit GOST block cipher (Magma) in counter mode.
More details in GOST R 34.12-2015 (RFC 8891) and GOST R 34.13-2015.

Directory structure

docs - diagrams and photos describing the project
prj - project files for different flows
src - Verilog HDL synthesizable sources
test - testbenches written in Python and Verilog

Required software

• Open-source flow (iCESugar-nano)
  • yosys (v0.34) (synthesis)
  • nextpnr (v0.6) (place & route)
  • icepack (bitstream generation)
  • icesprog (device programming and debug)
• Gowin flow (Tang Primer 20K)
  • Gowin EDA Education (v1.9.8.07)
• Xilinx flow (PYNQ-Z1)
  • Vivado (2020.2)
• Simulation
  • cocotb
  • pytest
  • Icarus Verilog
  • GTKWave (displays the .vcd waveforms generated by Icarus Verilog)

Starting up

1. Connect the PMOD microSD-card shield to the FPGA board the same way as on the photo.

2. Insert your microSD card in the shield and connect the FPGA board to the computer.

3. Switch directory to prj/<flow> where chosen flow depends on the board you're using.

4. Run make. This will run synthesis, place & route and generate a bitstream.

5. Program the device with make program (might require sudo).

6. Reset the design:

   • sudo make reset for iCESugar-nano
   • press button S3 for Tang Primer 20K
   • press button BTN3 for PYNQ-Z1

7. Start encryption/decryption:

   • sudo make start for iCESugar-nano
   • press button S4 for Tang Primer 20K
   • press button BTN2 for PYNQ-Z1

8. Wait until the LED will light up:

   • yellow on iCESugar-nano
   • LED 5 on Tang Primer 20K
   • LD2 on PYNQ-Z1

   It means that operation finished successfully.

9. You can check if operation failed by

   • running sudo make read_fail and looking if it returns 1 for iCESugar-nano
   • looking if LED 4 on Tang Primer 20K lighted up
   • looking if LD3 on PYNQ-Z1 lighted up

Simulation

• Run simulation for the whole design: SIM=icarus HDL_TOPLEVEL_LANG=verilog pytest test -s
• Run simulation for a specific module:
  1. cd test/<path to module's testbench>
  2. SIM=icarus HDL_TOPLEVEL_LANG=verilog pytest test_<module_name>.py -s
  3. open waveform: gtkwave sim_build/wave.vcd. After the window opens, Ctrl+O and select add_waves.gtkw file in the folder with the testbench.

Ports

Operating time

Flow	1 GB	2 GB	Blocks per transaction	OTP/SD clk (MHz)
Open-source	13m 23s	27m 4s	8	36/18
Gowin	5m 35s	10m 57s	16	175/50
Xilinx	3m 54s	6m 24s	128	175/50

TODO:

1. External memory support
2. SDHC and SDXC cards support