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Matlab/Simulink/XSG tool-flow for developing DSP systems for CASPER hardware
Verilog Matlab VHDL Tcl Makefile Python
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Pull request Compare This branch is 35 commits ahead, 174 commits behind casper-astro:master.
Latest commit 6d994c8 Apr 29, 2016 Paul Prozesky Allow workspace variables in sw_reg fields.
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