Patch Release v4.0.2

Description

• Fixes to support 64-bit addressing #113

Full Changelog: v4.0.1...v4.0.2

Patch Release v4.0.1

Pull Requests Since v4.0.0

Unlabeled

1. #110 - python/axipcie/_AxiPcieCore.py update
2. #111 - Fix typo in AxiPcieGpuAsyncControl

Pull Request Details

python/axipcie/_AxiPcieCore.py update

Author:	Larry Ruckman ruckman@slac.stanford.edu
Date:	Mon Mar 25 12:46:39 2024 -0700
Pull:	#110 (3 additions, 1 deletions, 1 files changed)
Branch:	slaclab/boardType-exception

Notes:

Description

• changing the self.boardType != PCIE_HW_TYPE_G from WARNING to ERROR w/ exception

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Fix typo in AxiPcieGpuAsyncControl

Author:	Larry Ruckman ruckman@slac.stanford.edu
Date:	Sat Apr 13 08:01:51 2024 -0700
Pull:	#111 (1 additions, 1 deletions, 1 files changed)
Branch:	slaclab/fix-gpuAsync-typo

Notes:

Fixes a tiny typo in GPU Async firmware

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v4.0.0

Description

• updating submodule locks
• removing support for SlacPgpCardG3
• switching BPI from P30 to MT28 (compatiable with S29GL)

Full Changelog: v3.15.0...v4.0.0

Minor Release v3.15.0

Pull Requests Since v3.14.0

Unlabeled

1. #97 - Add support for VU9P BittWareXupVv8 board.

Pull Request Details

Add support for VU9P BittWareXupVv8 board.

Author:	Larry Ruckman ruckman@slac.stanford.edu
Date:	Mon Feb 12 15:49:37 2024 -0800
Pull:	#97 (195 additions, 138 deletions, 12 files changed)
Branch:	slaclab/bittware-xcvu9p

Notes:

Description

• Tweak the XDC files to allow support for both versions of the board.

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v3.14.0

What's Changed

• adding support for hardware/AbacoPc821 by @ruck314 in #104
• Release Candidate v3.14.0 by @ruck314 in #105

Full Changelog: v3.13.0...v3.14.0

Minor Release v3.13.0

Description

• exposing BURST_BYTES_G/RD_PEND_THRESH_G and compromising/optimizing migDmaBuffer.vhd default for high rate & high bandwidth
• Update LICENSE.txt

Full Changelog: v3.12.1...v3.13.0

v3.12.1

What's Changed

• Update axi_ci.yml by @ruck314 in #101
• Release Candidate v3.12.1 by @ruck314 in #102

Full Changelog: v3.12.0...v3.12.1

v3.12.0

What's Changed

• Release Candidate v3.12.0 by @ruck314 in #100

Full Changelog: v3.11.3...v3.12.0

Patch Release v3.11.3

Pull Requests Since v3.11.2

Bug

1. #96 - Properly synchronize resets in AxiPcieReg

Pull Request Details

Properly synchronize resets in AxiPcieReg

Author:	Larry Ruckman ruckman@slac.stanford.edu
Date:	Mon Apr 3 13:33:31 2023 -0700
Pull:	#96 (39 additions, 17 deletions, 1 files changed)
Branch:	slaclab/reg-reset-fix
Labels:	bug

Notes:

The cardResetIn signal was not being synchronized to the correct clock.
Additionally, any reset signal created with an or gate needs to pass through a RstSync block.

Not yet tested so this is a draft PR.

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Patch Release v3.11.2

Description

• Update LICENSE.txt
• conda build test

Full Changelog: v3.11.1...v3.11.2