Update JTAG logic and testing infrastracture #177
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…y and NLP accelerators Add definition and link to generated RTL for Harvard U. Systolic Array, NLP and EdgeBERT accelerators
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Conflicts: .gitmodules accelerators/catapult_hls/common/systemc.mk rtl/sockets/jtag/jtag_test.vhd rtl/tiles/asic/asic_tile_acc.vhd rtl/tiles/asic/asic_tile_cpu.vhd rtl/tiles/asic/asic_tile_empty.vhd rtl/tiles/asic/asic_tile_io.vhd rtl/tiles/asic/asic_tile_mem.vhd rtl/tiles/asic/asic_tile_mem_ddr.vhd rtl/tiles/asic/asic_tile_slm.vhd rtl/tiles/asic/asic_tile_slm_ddr.vhd socs/epochs0-gf12/EPOCHS0_TOP.vhd socs/epochs0-gf12/fpga_proxy_top.vhd soft/ariane/opensbi tools/accgen/accgen.sh tools/socgen/esp_creator.py tools/socgen/esp_creator_batch.py tools/socgen/soc.py tools/socgen/socmap_gen.py utils/make/accelerators.mk utils/make/esp.mk utils/make/vivado.mk utils/toolchain/build_leon3_toolchain.sh utils/toolchain/build_riscv32imc_toolchain.sh utils/toolchain/build_riscv_toolchain.sh
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- Enable FPGA deployment of ASIC testing proxy with constraints and synthesis targets - Add FPGA emulation option for ASIC designs with dual-FPGA testing setup - Improvements to JTAG-based debug unit and accompanying testing flow Co-authored-by: Joseph Zuckerman <jzuck@cs.columbia.edu>
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