Naive i350 fixes

snabbco · Feb 9, 2018 · ddd90d2 · ddd90d2
1 parent 2ad3ed2
commit ddd90d2
Showing 1 changed file with 4 additions and 1 deletion.
diff --git a/src/apps/intel_mp/intel_mp.lua b/src/apps/intel_mp/intel_mp.lua
@@ -603,6 +603,7 @@ function Intel:load_registers(key)
 end
 function Intel:load_queue_registers(key)
   local v = reg[key]
+  if v.inherit then self:load_registers(v.inherit) end
   if v.txq and self.txq then
     register.define(v.txq, self.r, self.base, self.txq)
   end
@@ -1088,7 +1089,9 @@ function Intel1g:init_phy ()
    self.r.SW_FW_SYNC:clr(bits { SW_PHY_SM = 1 })
    self:unlock_fw_sem()
 
-   self.r.EEMNGCTL:wait(bits { CFG_DONE0 = 18 })
+-- NOTE: CFG_DONE0 does not necessarily correspond to PCI .0.
+-- E.g. on a PE720 2xI350 module, bits 20 & 21 are set for PCI .0 and .1 (not 18 & 19).
+--   self.r.EEMNGCTL:wait(bits { CFG_DONE0 = 18 })
 
    --[[
    self:lock_fw_sem()