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add transmit AFIFO
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@tmatsuya
tmatsuya committed Oct 1, 2013
1 parent d243627 commit dc6d508
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Showing 23 changed files with 1,717 additions and 36 deletions.
110 changes: 99 additions & 11 deletions boards/ecp3versa/rtl/ecp3/ethpipe_mid.v
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Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
module ethpipe_mid (
input clk_125
, input sys_rst
, output sys_intr
, output reg sys_intr = 1'b0
, input [7:0] dipsw
, output wire [7:0] led
, output [13:0] segled
Expand Down Expand Up @@ -35,8 +35,8 @@ module ethpipe_mid (
, input phy1_125M_clk
, input phy1_tx_clk
, output phy1_gtx_clk
, output phy1_tx_en
, output [7:0] phy1_tx_data
, output reg phy1_tx_en
, output reg [7:0] phy1_tx_data
, input phy1_rx_clk
, input phy1_rx_dv
, input phy1_rx_er
Expand All @@ -51,8 +51,8 @@ module ethpipe_mid (
, input phy2_125M_clk
, input phy2_tx_clk
, output phy2_gtx_clk
, output phy2_tx_en
, output [7:0] phy2_tx_data
, output reg phy2_tx_en
, output reg [7:0] phy2_tx_data
, input phy2_rx_clk
, input phy2_rx_dv
, input phy2_rx_er
Expand Down Expand Up @@ -190,6 +190,46 @@ gmii2fifo18 # (
);
`endif

// PHY#1 TX Transmite AFIFO
wire [8:0] tx1_phyq_din, tx1_phyq_dout;
wire tx1_phyq_full, tx1_phyq_wr_en;
wire tx1_phyq_empty;
reg tx1_phyq_rd_en = 1'b0;

afifo9 afifo9_tx1_phyq (
.Data(tx1_phyq_din),
.WrClock(clk_125),
.RdClock(phy1_125M_clk),
.WrEn(tx1_phyq_wr_en),
.RdEn(tx1_phyq_rd_en),
.Reset(sys_rst),
.RPReset(sys_rst),
.Q(tx1_phyq_dout),
.Empty(tx1_phyq_empty),
.Full(tx1_phyq_full)
);

// PHY#2 TX Transmite AFIFO
wire [8:0] tx2_phyq_din, tx2_phyq_dout;
wire tx2_phyq_full, tx2_phyq_wr_en;
wire tx2_phyq_empty;
reg tx2_phyq_rd_en = 1'b0;

`ifdef ENABLE_PHY2
afifo9 afifo9_tx2_phyq (
.Data(tx2_phyq_din),
.WrClock(clk_125),
.RdClock(phy2_125M_clk),
.WrEn(tx2_phyq_wr_en),
.RdEn(tx2_phyq_rd_en),
.Reset(sys_rst),
.RPReset(sys_rst),
.Q(tx2_phyq_dout),
.Empty(tx2_phyq_empty),
.Full(tx2_phyq_full)
);
`endif

// Slave bus
wire [6:0] slv_bar_i;
wire slv_ce_i;
Expand All @@ -208,6 +248,8 @@ wire [31:2] dma1_addr_cur, dma2_addr_cur;

reg dma1_load, dma2_load;

reg [15:0] intr_delay_val = 16'h1;

pcie_tlp inst_pcie_tlp (
// System
.pcie_clk(clk_125)
Expand Down Expand Up @@ -375,8 +417,8 @@ sender sender_phy1_ins (
, .global_counter(global_counter)

, .gmii_tx_clk(clk_125)
, .gmii_txd(phy1_tx_data)
, .gmii_tx_en(phy1_tx_en)
, .gmii_tx_din(tx1_phyq_din)
, .gmii_tx_wr(tx1_phyq_wr_en)
, .slot_tx_eth_data(tx0mem_dataB)
, .slot_tx_eth_byte_en(tx0mem_byte_enB)
, .slot_tx_eth_addr(tx0mem_addressB)
Expand Down Expand Up @@ -434,10 +476,10 @@ sender sender_phy2_ins (

assign phy1_mii_clk = 1'b0;
assign phy1_mii_data = 1'b0;
assign phy1_gtx_clk = clk_125;
assign phy1_gtx_clk = phy1_125M_clk;
assign phy2_mii_clk = 1'b0;
assign phy2_mii_data = 1'b0;
assign phy2_gtx_clk = clk_125;
assign phy2_gtx_clk = phy2_125M_clk;

// Global counter
always @(posedge clk_125) begin
Expand Down Expand Up @@ -474,6 +516,7 @@ always @(posedge clk_125) begin
local_time7 <= 48'h0;
local_time_update_pending <= 7'b0;
local_time_update_ack <= 1'b0;
intr_delay_val <= 16'h1;
end else begin

if (tx0local_time_req != 7'b0)
Expand All @@ -490,8 +533,15 @@ always @(posedge clk_125) begin
if (slv_bar_i[0] & slv_ce_i) begin
if (slv_adr_i[11:9] == 3'h0) begin
case (slv_adr_i[8:1])
// slots status
// interrupt delay clock (min:1 max:ffff)
8'h00: begin
if (slv_we_i) begin
if (slv_sel_i[1])
intr_delay_val[ 7: 0] <= slv_dat_i[15: 8];
if (slv_sel_i[0])
intr_delay_val[15: 8] <= slv_dat_i[ 7: 0];
end else
slv_dat0_o <= {intr_delay_val[7:0], intr_delay_val[15:8]};
end
// global counter [15:0]
8'h02: begin
Expand Down Expand Up @@ -716,9 +766,47 @@ always @(posedge clk_125) begin
end
end

//-------------------------------------
// GMII TX1 transmit from TX1_FIFO
//-------------------------------------
always @(posedge phy1_125M_clk) begin
if (sys_rst) begin
tx1_phyq_rd_en <= 1'b0;
phy1_tx_en <= 1'b0;
phy1_tx_data <= 8'b0;
end else begin
tx1_phyq_rd_en <= ~tx1_phyq_empty;
if (tx1_phyq_rd_en) begin
phy1_tx_data <= tx1_phyq_dout[7:0];
phy1_tx_en <= tx1_phyq_dout[8];
end else begin
phy1_tx_data <= 8'h0;
phy1_tx_en <= 1'b0;
end
end
end

reg [15:0] intr_delay_count = 16'h0000;
always @(posedge clk_125) begin
if (sys_rst) begin
sys_intr <= 1'b0;
intr_delay_count <= 16'h0000;
end else begin
if (dma_status[3] && intr_delay_count == 16'h0000) begin
intr_delay_count <= intr_delay_val;
end else begin
if (dma_status[3] == 1'b0)
sys_intr <= 1'b0;
else if (intr_delay_count == 16'h1)
sys_intr <= 1'b1;
if (intr_delay_count != 16'h0000)
intr_delay_count <= intr_delay_count - 16'h1;
end
end
end

assign slv_dat_o = ( {16{slv_bar_i[0]}} & slv_dat0_o ) | ( {16{slv_bar_i[2] & ~slv_adr_i[15]}} & slv_dat1_o ) | ( {16{slv_bar_i[2] & slv_adr_i[15]}} & slv_dat2_o );

assign sys_intr = dma_status[3];

endmodule

Expand Down
51 changes: 27 additions & 24 deletions boards/ecp3versa/rtl/ecp3/sender.v
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Original file line number Diff line number Diff line change
Expand Up @@ -9,8 +9,8 @@ module sender (

// GMII interfaces
, input wire gmii_tx_clk
, output reg [ 7:0] gmii_txd
, output reg gmii_tx_en
, output reg [ 8:0] gmii_tx_din
, output gmii_tx_wr

// TX frame slot
, output [15:0] slot_tx_eth_data
Expand Down Expand Up @@ -75,7 +75,7 @@ crc_gen tx_fcs_gen (
.Reset(sys_rst)
, .Clk(gmii_tx_clk)
, .Init(crc_init)
, .Frame_data(gmii_txd)
, .Frame_data(gmii_tx_din)
, .Data_en(crc_data_en)
, .CRC_rd(crc_rd)
, .CRC_end()
Expand Down Expand Up @@ -105,6 +105,7 @@ reg [13:0] rd_ptr;
/* packet sender logic */
always @(posedge gmii_tx_clk) begin
if (sys_rst) begin
gmii_tx_din[8:0] <= 9'h0;
tx_status <= 3'b0;
IFG_count <= 4'd0;
hdr_load_count <= 4'b0;
Expand All @@ -125,7 +126,7 @@ always @(posedge gmii_tx_clk) begin
debug5 <= 1'b0;
end else begin

gmii_tx_en <= 1'b0;
gmii_tx_din[8] <= 1'b0;
local_time_req <= 7'b0;

/* count Inter-frame Gap (12 clock) */
Expand Down Expand Up @@ -200,36 +201,36 @@ always @(posedge gmii_tx_clk) begin
/* transmit counter */
tx_counter <= tx_counter + 14'd1;

// gmii_tx_en
gmii_tx_en <= 1'b1;
// gmii_tx_wr
gmii_tx_din[8] <= 1'b1;

// gmii_txd
// gmii_tx_din
case (tx_counter)
14'd0: gmii_txd <= 8'h55; // preamble
14'd1: gmii_txd <= 8'h55;
14'd2: gmii_txd <= 8'h55;
14'd3: gmii_txd <= 8'h55;
14'd4: gmii_txd <= 8'h55;
14'd5: gmii_txd <= 8'h55;
14'd6: gmii_txd <= 8'h55;
14'd7: gmii_txd <= 8'hd5; // preamble+SFD
14'd0: gmii_tx_din[7:0] <= 8'h55; // preamble
14'd1: gmii_tx_din[7:0] <= 8'h55;
14'd2: gmii_tx_din[7:0] <= 8'h55;
14'd3: gmii_tx_din[7:0] <= 8'h55;
14'd4: gmii_tx_din[7:0] <= 8'h55;
14'd5: gmii_tx_din[7:0] <= 8'h55;
14'd6: gmii_tx_din[7:0] <= 8'h55;
14'd7: gmii_tx_din[7:0] <= 8'hd5; // preamble+SFD
default: begin
if (tx_counter[13:0] == tx_frame_len[13:0] + 14'd8) begin
tx_status <= TX_FCS_1;
slot_tx_eth_en <= 1'b0;
crc_rd <= 1'b1;
gmii_txd <= crc_out[31:24]; // ethernet FCS 0
gmii_tx_din[7:0] <= crc_out[31:24]; // ethernet FCS 0
end else begin
// send frame data
case (tx_counter[0])
1'b0: begin
gmii_txd <= slot_tx_eth_q[15:8];
gmii_tx_din[7:0] <= slot_tx_eth_q[15:8];
tx_data_tmp <= slot_tx_eth_q;
if (rd_ptr != mem_wr_ptr)
rd_ptr <= rd_ptr + 14'h1;
end
1'b1: begin
gmii_txd <= tx_data_tmp[7:0];
gmii_tx_din[7:0] <= tx_data_tmp[7:0];
end
endcase
end
Expand All @@ -238,18 +239,18 @@ always @(posedge gmii_tx_clk) begin
end
TX_FCS_1: begin // ethernet FCS 1
tx_status <= TX_FCS_2;
gmii_tx_en <= 1'b1;
gmii_txd <= crc_out[23:16];
gmii_tx_din[8] <= 1'b1;
gmii_tx_din[7:0] <= crc_out[23:16];
end
TX_FCS_2: begin // ethernet FCS 2
tx_status <= TX_FCS_3;
gmii_tx_en <= 1'b1;
gmii_txd <= crc_out[15:8];
gmii_tx_din[8] <= 1'b1;
gmii_tx_din[7:0] <= crc_out[15:8];
end
TX_FCS_3: begin // ethernet FCS 3
tx_status <= TX_IDLE;
gmii_tx_en <= 1'b1;
gmii_txd <= crc_out[7:0];
gmii_tx_din[8] <= 1'b1;
gmii_tx_din[7:0] <= crc_out[7:0];
// reset IFG_count
IFG_count <= 4'd0;
// update mem_rd_ptr
Expand Down Expand Up @@ -316,6 +317,8 @@ always @* begin
endcase
end

assign gmii_tx_wr = 1'b1; //(tx_status != TX_IDLE || IFG_count[3] == 1'b0);

/*
assign led[0] = (tx_status == TX_IDLE) ? 1'b0 : 1'b1;
assign led[1] = (tx_status == TX_HDR_LOAD) ? 1'b0 : 1'b1;
Expand Down
9 changes: 9 additions & 0 deletions boards/ecp3versa/rtl/ipexpress/ecp3/afifo9.ipx
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@@ -0,0 +1,9 @@
<?xml version="1.0" encoding="UTF-8"?>
<DiamondModule name="afifo9" module="FIFO_DC" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2013 10 02 00:43:36.892" version="5.5" type="Module" synthesis="synplify" source_format="Verilog">
<Package>
<File name="afifo9.lpc" type="lpc" modified="2013 10 02 00:43:34.739"/>
<File name="afifo9.v" type="top_level_verilog" modified="2013 10 02 00:43:34.848"/>
<File name="afifo9_tmpl.v" type="template_verilog" modified="2013 10 02 00:43:34.848"/>
<File name="tb_afifo9_tmpl.v" type="testbench_verilog" modified="2013 10 02 00:43:34.880"/>
</Package>
</DiamondModule>
47 changes: 47 additions & 0 deletions boards/ecp3versa/rtl/ipexpress/ecp3/afifo9.lpc
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Original file line number Diff line number Diff line change
@@ -0,0 +1,47 @@
[Device]
Family=latticeecp3
PartType=LFE3-35EA
PartName=LFE3-35EA-8FN484C
SpeedGrade=8
Package=FPBGA484
OperatingCondition=COM
Status=P

[IP]
VendorName=Lattice Semiconductor Corporation
CoreType=LPM
CoreStatus=Demo
CoreName=FIFO_DC
CoreRevision=5.5
ModuleName=afifo9
SourceFormat=Verilog HDL
ParameterFileVersion=1.0
Date=10/02/2013
Time=00:43:34

[Parameters]
Verilog=1
VHDL=0
EDIF=1
Destination=Synplicity
Expression=BusA(0 to 7)
Order=Big Endian [MSB:LSB]
IO=0
FIFOImp=EBR Based
Depth=16
Width=9
RDepth=16
RWidth=9
regout=0
CtrlByRdEn=0
EmpFlg=0
PeMode=Static - Dual Threshold
PeAssert=10
PeDeassert=12
FullFlg=0
PfMode=Static - Dual Threshold
PfAssert=508
PfDeassert=506
RDataCount=0
WDataCount=0
EnECC=0
26 changes: 26 additions & 0 deletions boards/ecp3versa/rtl/ipexpress/ecp3/afifo9.naf
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@@ -0,0 +1,26 @@
Data[8] i
Data[7] i
Data[6] i
Data[5] i
Data[4] i
Data[3] i
Data[2] i
Data[1] i
Data[0] i
WrClock i
RdClock i
WrEn i
RdEn i
Reset i
RPReset i
Q[8] o
Q[7] o
Q[6] o
Q[5] o
Q[4] o
Q[3] o
Q[2] o
Q[1] o
Q[0] o
Empty o
Full o
1 change: 1 addition & 0 deletions boards/ecp3versa/rtl/ipexpress/ecp3/afifo9.sort
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@@ -0,0 +1 @@
afifo9.v
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