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@riscv-steel

RISC-V Steel

riscv-steel
Netherlands

Hi, I'm Rafa (github.com/rafaelcalcada), a computer engineer from Brazil. I moved to the Netherlands two years ago to work for Siemens EDA. I love digital electronics and for the last 5 years I have been working on the development of RISC-V Steel.

RISC-V Steel was born in 2020 as the final project of my degree in computer engineering. My original goal was to develop a new, simple yet robust RISC-V processor core. At the end of that year I released the first version of RISC-V Steel and then graduated.

After its release RISC-V Steel gained attention on GitHub with daily visits and downloads. This motivated me to expand it into a free collection of hardware modules based on the RISC-V architecture. Memory, timers, UART, GPIO and SPI modules were added to the project, expanding the processor core into a microcontroller unit well suited for embedded applications.

By contributing you will be motivating me to work harder on RISC-V Steel!

@riscv-steel

Motivate me to work even harder. Buy equipament to test RISC-V Steel in new FPGA development boards.

Featured work

  1. riscv-steel/riscv-steel

    Free collection of hardware modules written in Verilog for FPGAs and embedded systems.

    Verilog 123

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