Two Address Instructions (16bit CPU)

Completely functional hardware unit realized as VHDL implementation of AOR2 project. This processor has modest possibilities and it can represent the core of a larger system, and can be be easy to upgrade it, improve its performance and embed it in any other complex application.

Structure

Repository is organized as following:

• doc directory contains assignment as well as solution document(s)
• source directory contains code

Tools needed

• Quartus 9.1
• ModelSim