memH: Require units for memory controller's 'backend.mem_size' parameter

sstsimulator · Sep 13, 2016 · c901abb · c901abb
1 parent 196bca3
commit c901abb
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Showing 18 changed files with 32 additions and 25 deletions.
diff --git a/src/sst/elements/memHierarchy/libmemHierarchy.cc b/src/sst/elements/memHierarchy/libmemHierarchy.cc
@@ -446,7 +446,7 @@ static Component* create_MemController(ComponentId_t id, Params& params){
 
 static const ElementInfoParam memctrl_params[] = {
     /* Required parameters */
-    {"backend.mem_size",    "Size of physical memory in MiB"},
+    {"backend.mem_size",    "Size of physical memory. NEW REQUIREMENT: must include units in 'B' (SI ok). Simple fix: add 'MiB' to old value."},
     {"clock",               "Clock frequency of controller", NULL},
     /* Optional parameters */
     {"backend",             "Timing backend to use:  Default to simpleMem", "memHierarchy.simpleMem"},

diff --git a/src/sst/elements/memHierarchy/membackend/dramSimBackend.cc b/src/sst/elements/memHierarchy/membackend/dramSimBackend.cc
@@ -25,13 +25,14 @@ DRAMSimMemory::DRAMSimMemory(Component *comp, Params &params) : MemBackend(comp,
         ctrl->dbg.fatal(CALL_INFO, -1, "Model must define a 'system_ini' file parameter\n");
 
 
-    unsigned int ramSize = params.find<unsigned int>("mem_size", 0);
-    if(0 == ramSize) {
-	ctrl->dbg.fatal(CALL_INFO, -1, "DRAMSim backend.mem_size parameter set to zero. Not allowed, must be power of two.\n");
+    UnitAlgebra ramSize = UnitAlgebra(params.find<std::string>("mem_size", "0B"));
+    if (ramSize.getRoundedValue() % (1024*1024) != 0) {
+        ctrl->dbg.fatal(CALL_INFO, -1, "For DRAMSim, backend.mem_size must be a multiple of 1MiB. Note: for units in base-10 use 'MB', for base-2 use 'MiB'. You specified '%s'\n", ramSize.toString().c_str());
     }
+    unsigned int ramSizeMiB = ramSize.getRoundedValue() / (1024*1024);
 
     memSystem = DRAMSim::getMemorySystemInstance(
-            deviceIniFilename, systemIniFilename, "", "", ramSize);
+            deviceIniFilename, systemIniFilename, "", "", ramSizeMiB);
 
     DRAMSim::Callback<DRAMSimMemory, void, unsigned int, uint64_t, uint64_t>
         *readDataCB, *writeDataCB;

diff --git a/src/sst/elements/memHierarchy/memoryController.cc b/src/sst/elements/memHierarchy/memoryController.cc
@@ -62,9 +62,9 @@ MemController::MemController(ComponentId_t id, Params &params) : Component(id) {
     if (found) {
         out.output("%s, **WARNING** ** Found deprecated parameter: statistics **  memHierarchy statistics have been moved to the Statistics API. Please see sst-info to view available statistics and update your input deck accordingly.\nNO statistics will be printed otherwise! Remove this parameter from your deck to eliminate this message.\n", getName().c_str());
     }
-    params.find<int>("mem_size", 0, found);
+    params.find<std::string>("mem_size", "0B", found);
     if (found) {
-        out.fatal(CALL_INFO, -1, "%s, Error - you specified memory size by the \"mem_size\" parameter, this must now be backend.mem_size, change the parameter name in your input deck.\n", getName().c_str());
+        out.fatal(CALL_INFO, -1, "%s, Error - you specified memory size by the \"mem_size\" parameter, this must now be backend.mem_size WITH UNITS (e.g., 8GiB or 1024MiB), change the parameter name in your input deck.\n", getName().c_str());
     }
     params.find<int>("network_num_vc", 0, found);
     if (found) {
@@ -80,9 +80,12 @@ MemController::MemController(ComponentId_t id, Params &params) : Component(id) {
     if (!found) {
         out.fatal(CALL_INFO, -1, "Param not specified (%s): clock - memory controller's clock rate (with units, e.g., MHz)\n", getName().c_str());
     }
-    const uint64_t backendRamSizeMB = params.find<uint64_t>("backend.mem_size", 0, found);
+    UnitAlgebra backendRamSize = UnitAlgebra(params.find<std::string>("backend.mem_size", "0B", found));
     if (!found) {
-        out.fatal(CALL_INFO, -1, "Param not specified (%s): backend.mem_size - memory controller must have a size specified (in MiBs)\n", getName().c_str());
+        out.fatal(CALL_INFO, -1, "Param not specified (%s): backend.mem_size - memory controller must have a size specified, (NEW) WITH units. E.g., 8GiB or 1024MiB. \n", getName().c_str());
+    }
+    if (!backendRamSize.hasUnits("B")) {
+        out.fatal(CALL_INFO, -1, "Invalid param (%s): backend.mem_size - definition has CHANGED! Now requires units in 'B' (SI OK, ex: 8GiB or 1024MiB).\nSince previous definition was implicitly MiB, you may simply append 'MiB' to the existing value. You specified '%s'\n", getName().c_str(), backendRamSize.toString().c_str());
     }
 
     rangeStart_             = params.find<Addr>("range_start", 0);
@@ -139,7 +142,10 @@ MemController::MemController(ComponentId_t id, Params &params) : Component(id) {
         dbg.fatal(CALL_INFO, -1, "Invalid param(%s): protocol - must be one of 'MESI', 'MSI', or 'NONE'. You specified '%s'\n", getName().c_str(), protocolStr.c_str());
     }
     // Convert into MBs
-    memSize_ = backendRamSizeMB * (1024*1024ul);
+    memSize_ = backendRamSize.getRoundedValue();
+    if (memSize_ % cacheLineSize_ != 0) {
+        dbg.fatal(CALL_INFO, -1, "Invalid param(%s): backend.mem_size - must be a multiple of request_size. Note: use 'MB' for base-10 and 'MiB' for base-2. Please change one of these parameters. You specified backend.mem_size='%s' and request_size='%d' B\n", getName().c_str(), backendRamSize.toString().c_str(), cacheLineSize_);
+    }
 
     // Check interleave parameters
     fixByteUnits(ilSize);

diff --git a/src/sst/elements/memHierarchy/tests/sdl-1.py b/src/sst/elements/memHierarchy/tests/sdl-1.py
@@ -32,7 +32,7 @@
       "debug" : "0",
       "backend.access_time" : "1000 ns",
       "clock" : "1GHz",
-      "backend.mem_size" : "512"
+      "backend.mem_size" : "512MiB"
 })
 
 # Enable statistics

diff --git a/src/sst/elements/memHierarchy/tests/sdl-2.py b/src/sst/elements/memHierarchy/tests/sdl-2.py
@@ -34,7 +34,7 @@
       "backend.access_time" : "100 ns",
       "backend.device_ini" : "DDR3_micron_32M_8B_x4_sg125.ini",
       "backend.system_ini" : "system.ini",
-      "backend.mem_size" : "512",
+      "backend.mem_size" : "512MiB",
       "request_width" : "32",
       "backend" : "memHierarchy.dramsim"
 })

diff --git a/src/sst/elements/memHierarchy/tests/sdl-3.py b/src/sst/elements/memHierarchy/tests/sdl-3.py
@@ -35,7 +35,7 @@
       "backend" : "memHierarchy.dramsim",
       "backend.system_ini" : "system.ini",
       "backend.device_ini" : "DDR3_micron_32M_8B_x4_sg125.ini",
-      "backend.mem_size" : "512"
+      "backend.mem_size" : "512MiB"
 })
 
 # Enable statistics

diff --git a/src/sst/elements/memHierarchy/tests/sdl2-1.py b/src/sst/elements/memHierarchy/tests/sdl2-1.py
@@ -45,7 +45,7 @@
       "debug" : "0",
       "backend.access_time" : "100 ns",
       "clock" : "1GHz",
-      "backend.mem_size" : "512"
+      "backend.mem_size" : "512MiB"
 })
 
 # Enable statistics

diff --git a/src/sst/elements/memHierarchy/tests/sdl3-1.py b/src/sst/elements/memHierarchy/tests/sdl3-1.py
@@ -66,7 +66,7 @@
 comp_memory.addParams({
       "coherence_protocol" : "MSI",
       "debug" : "0",
-      "backend.mem_size" : "512",
+      "backend.mem_size" : "512MiB",
       "printStats" : "1",
       "clock" : "1GHz",
       "backend.access_time" : "100 ns"

diff --git a/src/sst/elements/memHierarchy/tests/sdl3-2.py b/src/sst/elements/memHierarchy/tests/sdl3-2.py
@@ -67,7 +67,7 @@
       "coherence_protocol" : "MSI",
       "debug" : "0",
       "clock" : "1GHz",
-      "backend.mem_size" : "512",
+      "backend.mem_size" : "512MiB",
       "backend.access_time" : "100 ns",
       "backend.system_ini" : "system.ini",
       "backend.device_ini" : "DDR3_micron_32M_8B_x4_sg125.ini",

diff --git a/src/sst/elements/memHierarchy/tests/sdl3-3.py b/src/sst/elements/memHierarchy/tests/sdl3-3.py
@@ -63,7 +63,7 @@
 comp_memory.addParams({
       "coherence_protocol" : "MSI",
       "debug" : "0",
-      "backend.mem_size" : "512",
+      "backend.mem_size" : "512MiB",
       "printStats" : "1",
       "clock" : "1GHz",
       "backend.access_time" : "100 ns"

diff --git a/src/sst/elements/memHierarchy/tests/sdl4-1.py b/src/sst/elements/memHierarchy/tests/sdl4-1.py
@@ -66,7 +66,7 @@
       "debug" : "0",
       "backend.access_time" : "100 ns",
       "clock" : "1GHz",
-      "backend.mem_size" : "512"
+      "backend.mem_size" : "512MiB"
 })
 
 # Enable statistics

diff --git a/src/sst/elements/memHierarchy/tests/sdl4-2.py b/src/sst/elements/memHierarchy/tests/sdl4-2.py
@@ -64,7 +64,7 @@
       "coherence_protocol" : "MSI",
       "debug" : "0",
       "clock" : "1GHz",
-      "backend.mem_size" : "512",
+      "backend.mem_size" : "512MiB",
       "backend.access_time" : "100 ns",
       "backend.system_ini" : "system.ini",
       "backend.device_ini" : "DDR3_micron_32M_8B_x4_sg125.ini",

diff --git a/src/sst/elements/memHierarchy/tests/sdl5-1.py b/src/sst/elements/memHierarchy/tests/sdl5-1.py
@@ -139,7 +139,7 @@
       "coherence_protocol" : "MSI",
       "debug" : "0",
       "clock" : "1GHz",
-      "backend.mem_size" : "512",
+      "backend.mem_size" : "512MiB",
       "backend.access_time" : "1000 ns",
       "backend.system_ini" : "system.ini",
       "backend.device_ini" : "DDR3_micron_32M_8B_x4_sg125.ini",

diff --git a/src/sst/elements/memHierarchy/tests/sdl8-1.py b/src/sst/elements/memHierarchy/tests/sdl8-1.py
@@ -77,7 +77,7 @@
       "debug" : "0",
       "backend.access_time" : "100 ns",
       "clock" : "1GHz",
-      "backend.mem_size" : "512"
+      "backend.mem_size" : "512MiB"
 })
 
 # Enable statistics

diff --git a/src/sst/elements/memHierarchy/tests/sdl8-3.py b/src/sst/elements/memHierarchy/tests/sdl8-3.py
@@ -159,7 +159,7 @@
       "coherence_protocol" : "MSI",
       "debug" : "0",
       "backend.access_time" : "100 ns",
-      "backend.mem_size" : "512",
+      "backend.mem_size" : "512MiB",
       "clock" : "1GHz",
       "request_width" : "64"
 })

diff --git a/src/sst/elements/memHierarchy/tests/sdl8-4.py b/src/sst/elements/memHierarchy/tests/sdl8-4.py
@@ -165,7 +165,7 @@
       "debug" : "0",
       "backend.access_time" : "100 ns",
       "clock" : "1GHz",
-      "backend.mem_size" : "512",
+      "backend.mem_size" : "512MiB",
       "request_width" : "64"
 })
 

diff --git a/src/sst/elements/memHierarchy/tests/sdl9-1.py b/src/sst/elements/memHierarchy/tests/sdl9-1.py
@@ -58,7 +58,7 @@
       "debug" : "0",
       "backend.access_time" : "100 ns",
       "clock" : "1GHz",
-      "backend.mem_size" : "512"
+      "backend.mem_size" : "512MiB"
 })
 
 # Enable statistics

diff --git a/src/sst/elements/memHierarchy/tests/sdl9-2.py b/src/sst/elements/memHierarchy/tests/sdl9-2.py
@@ -250,7 +250,7 @@
       "debug" : "0",
       "backend.access_time" : "100 ns",
       "clock" : "1GHz",
-      "backend.mem_size" : "512"
+      "backend.mem_size" : "512MiB"
 })
 
 # Enable statistics