net/hns3: fix TM QCN error event report by MSI-X

[ upstream commit ffb6259 ]

The TM QCN error event should report by RAS other than MSIX.

Also this patch adds fifo int enable configuration before the TM QCN
error event is enabled.

Fixes: f53a793 ("net/hns3: add more hardware error types")
Fixes: 3903c05 ("net/hns3: remove read when enabling TM QCN error event")

Signed-off-by: Chengwen Feng <fengchengwen@huawei.com>
Signed-off-by: Min Hu (Connor) <humin29@huawei.com>

drivers/net/hns3/hns3_intr.c

@@ -1346,8 +1346,11 @@ enable_tm_err_intr(struct hns3_adapter *hns, bool en)
 
 	/* configure TM QCN hw errors */
 	hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_QCN_MEM_INT_CFG, false);
-	if (en)
+	desc.data[0] = rte_cpu_to_le_32(HNS3_TM_QCN_ERR_INT_TYPE);
+	if (en) {
+		desc.data[0] |= rte_cpu_to_le_32(HNS3_TM_QCN_FIFO_INT_EN);
 		desc.data[1] = rte_cpu_to_le_32(HNS3_TM_QCN_MEM_ERR_INT_EN);
+	}
 
 	ret = hns3_cmd_send(hw, &desc, 1);
 	if (ret)

drivers/net/hns3/hns3_intr.h

@@ -74,6 +74,8 @@
 #define HNS3_NCSI_ERR_INT_EN			0x3
 
 #define HNS3_TM_SCH_ECC_ERR_INT_EN		0x3
+#define HNS3_TM_QCN_ERR_INT_TYPE		0x29
+#define HNS3_TM_QCN_FIFO_INT_EN			0xFFFF00
 #define HNS3_TM_QCN_MEM_ERR_INT_EN		0xFFFFFF
 
 #define HNS3_RESET_PROCESS_MS			200