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vvp_process.c
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vvp_process.c
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/*
* Copyright (c) 2001-2005 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: vvp_process.c,v 1.126 2006/10/05 01:37:34 steve Exp $"
#endif
# include "vvp_priv.h"
# include <string.h>
# include <assert.h>
#ifdef HAVE_MALLOC_H
# include <malloc.h>
#endif
# include <stdlib.h>
static int show_statement(ivl_statement_t net, ivl_scope_t sscope);
unsigned local_count = 0;
unsigned thread_count = 0;
static unsigned transient_id = 0;
/*
* This file includes the code needed to generate VVP code for
* processes. Scopes are already declared, we generate here the
* executable code for the processes.
*/
unsigned bitchar_to_idx(char bit)
{
switch (bit) {
case '0':
return 0;
case '1':
return 1;
case 'x':
return 2;
case 'z':
return 3;
default:
assert(0);
return 0;
}
}
/*
* These functions handle the blocking assignment. Use the %set
* instruction to perform the actual assignment, and calculate any
* lvalues and rvalues that need calculating.
*
* The set_to_lvariable function takes a particular nexus and generates
* the %set statements to assign the value.
*
* The show_stmt_assign function looks at the assign statement, scans
* the l-values, and matches bits of the r-value with the correct
* nexus.
*/
static void set_to_lvariable(ivl_lval_t lval,
unsigned bit, unsigned wid)
{
ivl_signal_t sig = ivl_lval_sig(lval);
ivl_expr_t part_off_ex = ivl_lval_part_off(lval);
unsigned part_off = 0;
if (part_off_ex == 0) {
part_off = 0;
} else if (number_is_immediate(part_off_ex, 64)) {
part_off = get_number_immediate(part_off_ex);
part_off_ex = 0;
}
if (ivl_lval_mux(lval))
part_off_ex = ivl_lval_mux(lval);
if (part_off_ex) {
unsigned skip_set = transient_id++;
/* There is a mux expression, so this must be a write to
a bit-select l-val. Presumably, the x0 index register
has been loaded wit the result of the evaluated
part select base expression. */
draw_eval_expr_into_integer(part_off_ex, 0);
fprintf(vvp_out, " %%jmp/1 t_%u, 4;\n", skip_set);
fprintf(vvp_out, " %%set/x0 V_%s, %u, %u;\n",
vvp_signal_label(sig), bit, wid);
fprintf(vvp_out, "t_%u ;\n", skip_set);
} else if (part_off>0 || ivl_lval_width(lval)!=ivl_signal_width(sig)) {
/* There is no mux expression, but a constant part
offset. Load that into index x0 and generate a
vector set instruction. */
assert(ivl_lval_width(lval) == wid);
fprintf(vvp_out, " %%ix/load 0, %u;\n", part_off);
fprintf(vvp_out, " %%set/x0 V_%s, %u, %u;\n",
vvp_signal_label(sig), bit, wid);
} else {
save_signal_lookaside(bit, sig, wid);
fprintf(vvp_out, " %%set/v V_%s, %u, %u;\n",
vvp_signal_label(sig), bit, wid);
}
}
/*
* This function writes the code to set a vector to a memory word. The
* idx is the thread register that contains the address of the word in
* the memory, and bit is the base of the thread vector. The wid is
* the width of the vector to be written to the word.
*/
static void set_to_memory_word(ivl_lval_t lval, unsigned idx,
unsigned bit, unsigned wid)
{
unsigned skip_set = transient_id++;
ivl_memory_t mem = ivl_lval_mem(lval);
/* Calculate the word part select into index-1 */
if (ivl_lval_part_off(lval)) {
draw_eval_expr_into_integer(ivl_lval_part_off(lval), 1);
fprintf(vvp_out, " %%jmp/1 t_%u, 4;\n", skip_set);
} else {
fprintf(vvp_out, " %%ix/load 1, 0;\n");
}
/* Calculate the memory address into index-3 */
draw_memory_index_expr(mem, ivl_lval_idx(lval));
fprintf(vvp_out, " %%jmp/1 t_%u, 4;\n", skip_set);
fprintf(vvp_out, " %%set/mv M_%p, %u, %u;\n", mem, bit, wid);
fprintf(vvp_out, "t_%u ;\n", skip_set);
}
static void assign_to_lvector(ivl_lval_t lval, unsigned bit,
unsigned delay, ivl_expr_t dexp,
unsigned width)
{
ivl_signal_t sig = ivl_lval_sig(lval);
ivl_expr_t part_off_ex = ivl_lval_part_off(lval);
unsigned part_off = 0;
if (part_off_ex == 0) {
part_off = 0;
} else if (number_is_immediate(part_off_ex, 64)) {
part_off = get_number_immediate(part_off_ex);
part_off_ex = 0;
}
if (ivl_lval_mux(lval))
part_off_ex = ivl_lval_mux(lval);
if (part_off_ex) {
unsigned skip_assign = transient_id++;
assert(dexp == 0);
draw_eval_expr_into_integer(part_off_ex, 1);
/* If the index expression has XZ bits, skip the assign. */
fprintf(vvp_out, " %%jmp/1 t_%u, 4;\n", skip_assign);
fprintf(vvp_out, " %%ix/load 0, %u;\n", width);
fprintf(vvp_out, " %%assign/v0/x1 V_%s, %u, %u;\n",
vvp_signal_label(sig), delay, bit);
fprintf(vvp_out, "t_%u ;\n", skip_assign);
} else if (part_off>0 || ivl_lval_width(lval)!=ivl_signal_width(sig)) {
/* There is no mux expression, but a constant part
offset. Load that into index x1 and generate a
single-bit set instruction. */
assert(ivl_lval_width(lval) == width);
if (dexp == 0) {
/* Constant delay... */
fprintf(vvp_out, " %%ix/load 0, %u;\n", width);
fprintf(vvp_out, " %%ix/load 1, %u;\n", part_off);
fprintf(vvp_out, " %%assign/v0/x1 V_%s, %u, %u;\n",
vvp_signal_label(sig), delay, bit);
} else {
/* Calculated delay... */
int delay_index = allocate_word();
draw_eval_expr_into_integer(dexp, delay_index);
fprintf(vvp_out, " %%ix/load 0, %u;\n", width);
fprintf(vvp_out, " %%ix/load 1, %u;\n", part_off);
fprintf(vvp_out, " %%assign/v0/x1/d V_%s, %u, %u;\n",
vvp_signal_label(sig), delay_index, bit);
clr_word(delay_index);
}
} else if (dexp != 0) {
draw_eval_expr_into_integer(dexp, 1);
fprintf(vvp_out, " %%ix/load 0, %u;\n", width);
fprintf(vvp_out, " %%assign/v0/d V_%s, 1, %u;\n",
vvp_signal_label(sig), bit);
} else {
fprintf(vvp_out, " %%ix/load 0, %u;\n", width);
fprintf(vvp_out, " %%assign/v0 V_%s, %u, %u;\n",
vvp_signal_label(sig), delay, bit);
}
}
static void assign_to_memory_word(ivl_lval_t lval, unsigned bit,
unsigned delay, unsigned wid)
{
unsigned skip_set = transient_id++;
ivl_memory_t mem = ivl_lval_mem(lval);
//assert(wid == ivl_memory_width(mem));
/* Calculate the word part select into index-1 */
if (ivl_lval_part_off(lval)) {
draw_eval_expr_into_integer(ivl_lval_part_off(lval), 1);
fprintf(vvp_out, " %%jmp/1 t_%u, 4;\n", skip_set);
} else {
fprintf(vvp_out, " %%ix/load 1, 0;\n");
}
/* Calculate the memory address into index-3 */
draw_memory_index_expr(mem, ivl_lval_idx(lval));
fprintf(vvp_out, " %%jmp/1 t_%u, 4;\n", skip_set);
/* Load the word/part-select width into index-0 */
fprintf(vvp_out, " %%ix/load 0, %u;\n", wid);
fprintf(vvp_out, " %%assign/mv M_%p, %u, %u;\n", mem, delay, bit);
fprintf(vvp_out, "t_%u ;\n", skip_set);
clear_expression_lookaside();
}
/*
* This is a private function to generate %set code for the
* statement. At this point, the r-value is evaluated and stored in
* the res vector, I just need to generate the %set statements for the
* l-values of the assignment.
*/
static void set_vec_to_lval(ivl_statement_t net, struct vector_info res)
{
ivl_lval_t lval;
ivl_memory_t mem;
unsigned wid = res.wid;
unsigned lidx;
unsigned cur_rbit = 0;
for (lidx = 0 ; lidx < ivl_stmt_lvals(net) ; lidx += 1) {
unsigned bidx;
unsigned bit_limit = wid - cur_rbit;
lval = ivl_stmt_lval(net, lidx);
mem = ivl_lval_mem(lval);
/* Reduce bit_limit to the width of this l-value. */
if (bit_limit > ivl_lval_width(lval))
bit_limit = ivl_lval_width(lval);
/* This is the address within the larger r-value of the
bit that this l-value takes. */
bidx = res.base < 4? res.base : (res.base+cur_rbit);
if (mem) {
set_to_memory_word(lval, 3, bidx, bit_limit);
} else {
set_to_lvariable(lval, bidx, bit_limit);
}
/* Now we've consumed this many r-value bits for the
current l-value. */
cur_rbit += bit_limit;
}
}
static int show_stmt_assign_vector(ivl_statement_t net)
{
ivl_expr_t rval = ivl_stmt_rval(net);
/* Handle the special case that the expression is a real
value. Evaluate the real expression, then convert the
result to a vector. Then store that vector into the
l-value. */
if (ivl_expr_value(rval) == IVL_VT_REAL) {
int word = draw_eval_real(rval);
/* This is the accumulated with of the l-value of the
assignment. */
unsigned wid = ivl_stmt_lwidth(net);
struct vector_info vec;
vec.base = allocate_vector(wid);
vec.wid = wid;
fprintf(vvp_out, " %%cvt/vr %u, %d, %u;\n",
vec.base, word, vec.wid);
clr_word(word);
set_vec_to_lval(net, vec);
clr_vector(vec);
return 0;
}
{ struct vector_info res = draw_eval_expr(rval, 0);
set_vec_to_lval(net, res);
if (res.base > 3)
clr_vector(res);
}
return 0;
}
/*
* This function assigns a value to a real .variable. This is destined
* for /dev/null when typed ivl_signal_t takes over all the real
* variable support.
*/
static int show_stmt_assign_sig_real(ivl_statement_t net)
{
int res;
ivl_lval_t lval;
ivl_signal_t var;
res = draw_eval_real(ivl_stmt_rval(net));
clr_word(res);
assert(ivl_stmt_lvals(net) == 1);
lval = ivl_stmt_lval(net, 0);
var = ivl_lval_sig(lval);
assert(var != 0);
fprintf(vvp_out, " %%set/wr V_%s, %d;\n",
vvp_signal_label(var), res);
return 0;
}
static int show_stmt_assign(ivl_statement_t net)
{
ivl_lval_t lval;
ivl_signal_t sig;
lval = ivl_stmt_lval(net, 0);
sig = ivl_lval_sig(lval);
if (sig) switch (ivl_signal_data_type(sig)) {
case IVL_VT_REAL:
return show_stmt_assign_sig_real(net);
default:
return show_stmt_assign_vector(net);
} else {
return show_stmt_assign_vector(net);
}
return 0;
}
/*
* This function handles the case of non-blocking assign to word
* variables such as real, i.e:
*
* real foo;
* foo <= 1.0;
*
* In this case we know (by Verilog syntax) that there is only exactly
* 1 l-value, the target identifier, so it should be relatively easy.
*/
static int show_stmt_assign_nb_real(ivl_statement_t net)
{
ivl_lval_t lval;
ivl_signal_t sig;
ivl_expr_t rval = ivl_stmt_rval(net);
ivl_expr_t del = ivl_stmt_delay_expr(net);
int word;
unsigned long delay;
/* Must be exactly 1 l-value. */
assert(ivl_stmt_lvals(net) == 1);
delay = 0;
if (del && (ivl_expr_type(del) == IVL_EX_ULONG)) {
delay = ivl_expr_uvalue(del);
del = 0;
}
/* XXXX For now, presume delays are constant. */
assert(del == 0);
/* Evaluate the r-value */
word = draw_eval_real(rval);
lval = ivl_stmt_lval(net, 0);
sig = ivl_lval_sig(lval);
assert(sig);
fprintf(vvp_out, " %%assign/wr V_%s, %lu, %u;\n",
vvp_signal_label(sig), delay, word);
clr_word(word);
return 0;
}
static int show_stmt_assign_nb(ivl_statement_t net)
{
ivl_lval_t lval;
ivl_expr_t rval = ivl_stmt_rval(net);
ivl_expr_t del = ivl_stmt_delay_expr(net);
ivl_memory_t mem;
ivl_signal_t sig;
unsigned long delay = 0;
/* Detect special cases that are handled elsewhere. */
lval = ivl_stmt_lval(net,0);
if ((sig = ivl_lval_sig(lval))) {
switch (ivl_signal_data_type(sig)) {
case IVL_VT_REAL:
return show_stmt_assign_nb_real(net);
default:
break;
}
}
if (del && (ivl_expr_type(del) == IVL_EX_ULONG)) {
delay = ivl_expr_uvalue(del);
del = 0;
}
{ struct vector_info res = draw_eval_expr(rval, 0);
unsigned wid = res.wid;
unsigned lidx;
unsigned cur_rbit = 0;
for (lidx = 0 ; lidx < ivl_stmt_lvals(net) ; lidx += 1) {
unsigned bit_limit = wid - cur_rbit;
lval = ivl_stmt_lval(net, lidx);
mem = ivl_lval_mem(lval);
if (bit_limit > ivl_lval_width(lval))
bit_limit = ivl_lval_width(lval);
if (mem == 0) {
unsigned bidx;
bidx = res.base < 4? res.base : (res.base+cur_rbit);
assign_to_lvector(lval, bidx, delay, del, bit_limit);
} else {
unsigned bidx;
/* XXXX don't yet know what to do with a
non-constant delay exprssion. */
assert(del == 0);
bidx = res.base < 4? res.base : (res.base+cur_rbit);
assign_to_memory_word(lval, bidx, delay, bit_limit);
}
cur_rbit += bit_limit;
}
if (res.base > 3)
clr_vector(res);
}
return 0;
}
static int show_stmt_block(ivl_statement_t net, ivl_scope_t sscope)
{
int rc = 0;
unsigned idx;
unsigned cnt = ivl_stmt_block_count(net);
for (idx = 0 ; idx < cnt ; idx += 1) {
rc += show_statement(ivl_stmt_block_stmt(net, idx), sscope);
}
return rc;
}
/*
* This draws an invocation of a named block. This is a little
* different because a subscope is created. We do that by creating
* a thread to deal with this.
*/
static int show_stmt_block_named(ivl_statement_t net, ivl_scope_t scope)
{
int rc;
int out_id, sub_id;
ivl_scope_t subscope = ivl_stmt_block_scope(net);
out_id = transient_id++;
sub_id = transient_id++;
fprintf(vvp_out, " %%fork t_%u, S_%p;\n",
sub_id, subscope);
fprintf(vvp_out, " %%jmp t_%u;\n", out_id);
fprintf(vvp_out, "t_%u ;\n", sub_id);
rc = show_stmt_block(net, subscope);
fprintf(vvp_out, " %%end;\n");
fprintf(vvp_out, "t_%u %%join;\n", out_id);
clear_expression_lookaside();
return rc;
}
static int show_stmt_case(ivl_statement_t net, ivl_scope_t sscope)
{
ivl_expr_t exp = ivl_stmt_cond_expr(net);
struct vector_info cond = draw_eval_expr(exp, 0);
unsigned count = ivl_stmt_case_count(net);
unsigned local_base = local_count;
unsigned idx, default_case;
local_count += count + 1;
/* First draw the branch table. All the non-default cases
generate a branch out of here, to the code that implements
the case. The default will fall through all the tests. */
default_case = count;
for (idx = 0 ; idx < count ; idx += 1) {
ivl_expr_t cex = ivl_stmt_case_expr(net, idx);
struct vector_info cvec;
if (cex == 0) {
default_case = idx;
continue;
}
/* Is the guard expression something I can pass to a
%cmpi/u instruction? If so, use that instead. */
if ((ivl_statement_type(net) == IVL_ST_CASE)
&& (ivl_expr_type(cex) == IVL_EX_NUMBER)
&& (! number_is_unknown(cex))
&& number_is_immediate(cex, 16)) {
unsigned long imm = get_number_immediate(cex);
fprintf(vvp_out, " %%cmpi/u %u, %lu, %u;\n",
cond.base, imm, cond.wid);
fprintf(vvp_out, " %%jmp/1 T_%d.%d, 6;\n",
thread_count, local_base+idx);
continue;
}
/* Oh well, do this case the hard way. */
cvec = draw_eval_expr_wid(cex, cond.wid, STUFF_OK_RO);
assert(cvec.wid == cond.wid);
switch (ivl_statement_type(net)) {
case IVL_ST_CASE:
fprintf(vvp_out, " %%cmp/u %u, %u, %u;\n",
cond.base, cvec.base, cond.wid);
fprintf(vvp_out, " %%jmp/1 T_%d.%d, 6;\n",
thread_count, local_base+idx);
break;
case IVL_ST_CASEX:
fprintf(vvp_out, " %%cmp/x %u, %u, %u;\n",
cond.base, cvec.base, cond.wid);
fprintf(vvp_out, " %%jmp/1 T_%d.%d, 4;\n",
thread_count, local_base+idx);
break;
case IVL_ST_CASEZ:
fprintf(vvp_out, " %%cmp/z %u, %u, %u;\n",
cond.base, cvec.base, cond.wid);
fprintf(vvp_out, " %%jmp/1 T_%d.%d, 4;\n",
thread_count, local_base+idx);
break;
default:
assert(0);
}
/* Done with the case expression */
clr_vector(cvec);
}
/* Done with the condition expression */
clr_vector(cond);
/* Emit code for the default case. */
if (default_case < count) {
ivl_statement_t cst = ivl_stmt_case_stmt(net, default_case);
show_statement(cst, sscope);
}
/* Jump to the out of the case. */
fprintf(vvp_out, " %%jmp T_%d.%d;\n", thread_count,
local_base+count);
for (idx = 0 ; idx < count ; idx += 1) {
ivl_statement_t cst = ivl_stmt_case_stmt(net, idx);
if (idx == default_case)
continue;
fprintf(vvp_out, "T_%d.%d ;\n", thread_count, local_base+idx);
clear_expression_lookaside();
show_statement(cst, sscope);
fprintf(vvp_out, " %%jmp T_%d.%d;\n", thread_count,
local_base+count);
}
/* The out of the case. */
fprintf(vvp_out, "T_%d.%d ;\n", thread_count, local_base+count);
clear_expression_lookaside();
return 0;
}
static int show_stmt_case_r(ivl_statement_t net, ivl_scope_t sscope)
{
ivl_expr_t exp = ivl_stmt_cond_expr(net);
int cond = draw_eval_real(exp);
unsigned count = ivl_stmt_case_count(net);
unsigned local_base = local_count;
unsigned idx, default_case;
local_count += count + 1;
/* First draw the branch table. All the non-default cases
generate a branch out of here, to the code that implements
the case. The default will fall through all the tests. */
default_case = count;
for (idx = 0 ; idx < count ; idx += 1) {
ivl_expr_t cex = ivl_stmt_case_expr(net, idx);
int cvec;
if (cex == 0) {
default_case = idx;
continue;
}
cvec = draw_eval_real(cex);
fprintf(vvp_out, " %%cmp/wr %d, %d;\n", cond, cvec);
fprintf(vvp_out, " %%jmp/1 T_%d.%d, 4;\n",
thread_count, local_base+idx);
/* Done with the guard expression value. */
clr_word(cvec);
}
/* Done with the case expression. */
clr_word(cond);
/* Emit code for the case default. The above jump table will
fall through to this statement. */
if (default_case < count) {
ivl_statement_t cst = ivl_stmt_case_stmt(net, default_case);
show_statement(cst, sscope);
}
/* Jump to the out of the case. */
fprintf(vvp_out, " %%jmp T_%d.%d;\n", thread_count,
local_base+count);
for (idx = 0 ; idx < count ; idx += 1) {
ivl_statement_t cst = ivl_stmt_case_stmt(net, idx);
if (idx == default_case)
continue;
fprintf(vvp_out, "T_%d.%d ;\n", thread_count, local_base+idx);
clear_expression_lookaside();
show_statement(cst, sscope);
fprintf(vvp_out, " %%jmp T_%d.%d;\n", thread_count,
local_base+count);
}
/* The out of the case. */
fprintf(vvp_out, "T_%d.%d ;\n", thread_count, local_base+count);
return 0;
}
static void force_vector_to_lval(ivl_statement_t net, struct vector_info rvec)
{
unsigned lidx;
unsigned roff = 0;
const char*command_name;
const char*command_name_x0;
switch (ivl_statement_type(net)) {
case IVL_ST_CASSIGN:
command_name = "%cassign/v";
command_name_x0 = "ERROR";
break;
case IVL_ST_FORCE:
command_name = "%force/v";
command_name_x0 = "%force/x0";
break;
default:
command_name = "ERROR";
assert(0);
break;
}
for (lidx = 0 ; lidx < ivl_stmt_lvals(net) ; lidx += 1) {
ivl_lval_t lval = ivl_stmt_lval(net, lidx);
ivl_signal_t lsig = ivl_lval_sig(lval);
unsigned use_wid = ivl_lval_width(lval);
ivl_expr_t part_off_ex = ivl_lval_part_off(lval);
unsigned part_off;
if (part_off_ex == 0) {
part_off = 0;
} else {
assert(number_is_immediate(part_off_ex, 64));
part_off = get_number_immediate(part_off_ex);
}
/* L-Value must be a signal: reg or wire */
assert(lsig != 0);
if (part_off != 0 || use_wid != ivl_signal_width(lsig)) {
command_name = command_name_x0;
fprintf(vvp_out, " %%ix/load 0, %u;\n", part_off);
} else {
/* Do not support bit or part selects of l-values yet. */
assert(ivl_lval_mux(lval) == 0);
assert(ivl_lval_part_off(lval) == 0);
assert(ivl_lval_width(lval) == ivl_signal_width(lsig));
assert((roff + use_wid) <= rvec.wid);
}
fprintf(vvp_out, " %s V_%s, %u, %u;\n", command_name,
vvp_signal_label(lsig), rvec.base+roff, use_wid);
if (rvec.base >= 4)
roff += use_wid;
}
}
static void force_link_rval(ivl_statement_t net, ivl_expr_t rval)
{
ivl_signal_t rsig;;
ivl_lval_t lval;
ivl_signal_t lsig;
const char*command_name;
if (ivl_expr_type(rval) != IVL_EX_SIGNAL)
return;
switch (ivl_statement_type(net)) {
case IVL_ST_CASSIGN:
command_name = "%cassign";
break;
case IVL_ST_FORCE:
command_name = "%force";
break;
default:
command_name = "ERROR";
assert(0);
break;
}
rsig = ivl_expr_signal(rval);
assert(ivl_stmt_lvals(net) == 1);
lval = ivl_stmt_lval(net, 0);
lsig = ivl_lval_sig(lval);
fprintf(vvp_out, " %s/link", command_name);
fprintf(vvp_out, " V_%s", vvp_signal_label(lsig));
fprintf(vvp_out, ", V_%s;\n", vvp_signal_label(rsig));
}
static int show_stmt_cassign(ivl_statement_t net)
{
ivl_expr_t rval;
struct vector_info rvec;
rval = ivl_stmt_rval(net);
assert(rval);
rvec = draw_eval_expr(rval, STUFF_OK_47);
/* Write out initial continuous assign instructions to assign
the expression value to the l-value. */
force_vector_to_lval(net, rvec);
force_link_rval(net, rval);
return 0;
}
/*
* Handle the deassign similar to cassign. The lvals must all be
* vectors without bit or part selects. Simply call %deassign for all
* the values.
*/
static int show_stmt_deassign(ivl_statement_t net)
{
unsigned lidx;
for (lidx = 0 ; lidx < ivl_stmt_lvals(net) ; lidx += 1) {
ivl_lval_t lval = ivl_stmt_lval(net, lidx);
ivl_signal_t lsig = ivl_lval_sig(lval);
assert(lsig != 0);
assert(ivl_lval_mux(lval) == 0);
assert(ivl_lval_part_off(lval) == 0);
fprintf(vvp_out, " %%deassign V_%s;\n", vvp_signal_label(lsig));
}
return 0;
}
static int show_stmt_condit(ivl_statement_t net, ivl_scope_t sscope)
{
int rc = 0;
unsigned lab_false, lab_out;
ivl_expr_t exp = ivl_stmt_cond_expr(net);
struct vector_info cond
= draw_eval_expr(exp, STUFF_OK_XZ|STUFF_OK_47|STUFF_OK_RO);
assert(cond.wid == 1);
lab_false = local_count++;
lab_out = local_count++;
fprintf(vvp_out, " %%jmp/0xz T_%d.%d, %u;\n",
thread_count, lab_false, cond.base);
/* Done with the condition expression. */
if (cond.base >= 8)
clr_vector(cond);
if (ivl_stmt_cond_true(net))
rc += show_statement(ivl_stmt_cond_true(net), sscope);
if (ivl_stmt_cond_false(net)) {
fprintf(vvp_out, " %%jmp T_%d.%d;\n", thread_count, lab_out);
fprintf(vvp_out, "T_%d.%u ;\n", thread_count, lab_false);
clear_expression_lookaside();
rc += show_statement(ivl_stmt_cond_false(net), sscope);
fprintf(vvp_out, "T_%d.%u ;\n", thread_count, lab_out);
clear_expression_lookaside();
} else {
fprintf(vvp_out, "T_%d.%u ;\n", thread_count, lab_false);
clear_expression_lookaside();
}
return rc;
}
/*
* The delay statement is easy. Simply write a ``%delay <n>''
* instruction to delay the thread, then draw the included statement.
* The delay statement comes from verilog code like this:
*
* ...
* #<delay> <stmt>;
*/
static int show_stmt_delay(ivl_statement_t net, ivl_scope_t sscope)
{
int rc = 0;
uint64_t delay = ivl_stmt_delay_val(net);
ivl_statement_t stmt = ivl_stmt_sub_stmt(net);
unsigned long low = delay % UINT64_C(0x100000000);
unsigned long hig = delay / UINT64_C(0x100000000);
fprintf(vvp_out, " %%delay %lu, %lu;\n", low, hig);
/* Lots of things can happen during a delay. */
clear_expression_lookaside();
rc += show_statement(stmt, sscope);
return rc;
}
/*
* The delayx statement is slightly more complex in that it is
* necessary to calculate the delay first. Load the calculated delay
* into and index register and use the %delayx instruction to do the
* actual delay.
*/
static int show_stmt_delayx(ivl_statement_t net, ivl_scope_t sscope)
{
int rc = 0;
ivl_expr_t exp = ivl_stmt_delay_expr(net);
ivl_statement_t stmt = ivl_stmt_sub_stmt(net);
switch (ivl_expr_value(exp)) {
case IVL_VT_BOOL:
case IVL_VT_LOGIC: {
struct vector_info del = draw_eval_expr(exp, 0);
fprintf(vvp_out, " %%ix/get 0, %u, %u;\n",
del.base, del.wid);
clr_vector(del);
break;
}
case IVL_VT_REAL: {
int word = draw_eval_real(exp);
fprintf(vvp_out, " %%cvt/ir 0, %d;\n", word);
clr_word(word);
break;
}
default:
assert(0);
}
fprintf(vvp_out, " %%delayx 0;\n");
/* Lots of things can happen during a delay. */
clear_expression_lookaside();
rc += show_statement(stmt, sscope);
return rc;
}
static int show_stmt_disable(ivl_statement_t net, ivl_scope_t sscope)
{
int rc = 0;
ivl_scope_t target = ivl_stmt_call(net);
fprintf(vvp_out, " %%disable S_%p;\n", target);
return rc;
}
static int show_stmt_force(ivl_statement_t net)
{
ivl_expr_t rval;
struct vector_info rvec;
rval = ivl_stmt_rval(net);
assert(rval);
rvec = draw_eval_expr(rval, STUFF_OK_47);
/* Write out initial continuous assign instructions to assign
the expression value to the l-value. */
force_vector_to_lval(net, rvec);
force_link_rval(net, rval);
return 0;
}
static int show_stmt_forever(ivl_statement_t net, ivl_scope_t sscope)