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ivl_target.h
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ivl_target.h
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#ifndef __ivl_target_H
#define __ivl_target_H
/*
* Copyright (c) 2000-2004 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: ivl_target.h,v 1.174 2007/01/17 05:00:12 steve Exp $"
#endif
# include <stdint.h>
#ifdef __cplusplus
#define _BEGIN_DECL extern "C" {
#define _END_DECL }
#else
#define _BEGIN_DECL
#define _END_DECL
#endif
_BEGIN_DECL
/*
* This header file describes the API for the loadable target
* module. The main program can load these modules and access the
* functions within the loaded module to implement the backend
* behavior.
*
* The interface is divided into two parts: the entry points within
* the core that are called by the module, and the entry points in
* the module that are called by the core. It is the latter that
* causes the module to be invoked in the first place, but most of the
* interesting information about the design is accessed through the
* various access functions that the modules calls into the core.
*/
/*
* In order to grab onto data in the design, the core passes cookies
* to the various functions of the module. These cookies can in turn
* be passed to access functions in the core to get more detailed
* information.
*
* The following typedefs list the various cookies that may be passed
* around.
*
* ivl_array_t
* This object represent an array that can be a memory or a net
* array. (They are the same from the perspective of ivl_target.h.)
*
* ivl_design_t
* This object represents the entire elaborated design. Various
* global properties and methods are available from this.
*
* ivl_event_t
* This object represents an event node. An event node stands for
* named events written explicitly in the Verilog, and net events
* that are implicit when @ statements are used.
*
* ivl_expr_t
* This object represents a node of an expression. If the
* expression has sub-expressions, they can be accessed from
* various method described below. The ivl_expr_type method in
* particular gets the type of the node in the form of an
* ivl_expr_type_t enumeration value.
*
* Objects of this type represent expressions in
* processes. Structural expressions are instead treated as logic
* gates.
*
* ivl_lpm_t
* This object is the base class for all the various LPM type
* device nodes. This object carries a few base properties
* (including a type) including a handle to the specific type.
*
* ivl_net_logic_t
* This object represents various built in logic devices. In fact,
* this includes just about every directional device that has a
* single output, including logic gates and nmos, pmos and cmos
* devices. There is also the occasional Icarus Verilog creation.
* What is common about these devices is that they are
* bitwise. That is, when fed a vector, they produce a vector
* result where each bit of the output is made only from the same
* bits in the vector inputs.
*
* ivl_nexus_t
* Structural links within an elaborated design are connected
* together at each bit. The connection point is a nexus, so pins
* of devices refer to an ivl_nexus_t. Furthermore, from a nexus
* there are backward references to all the device pins that point
* to it.
*
* ivl_parameter_t
* Scopes have zero or more parameter objects that represent
* parameters that the source defined. The parameter has a value
* that is fully elaborated, with defparams and other parameter
* overrides taken care of.
*
* ivl_process_t
* A Verilog process is represented by one of these. A process may
* be an "initial" or an "always" process. These come from initial
* or always statements from the Verilog source.
*
* ivl_scope_t
* Elaborated scopes within a design are represented by this
* type. Objects of this type also act as containers for scoped
* objects such as signals.
*
* ivl_statement_t
* Statements within processes are represented by one of these. The
* ivl_process_t object holds one of these, but a statement may in
* turn contain other statements.
*
* -- A Note About Bit Sets --
* Some objects hold a value as an array of bits. In these cases there
* is some method that retrieves the width of the value and another
* that returns a "char*". The latter is a pointer to the least
* significant bit value. Bit values are represented by the characters
* '0', '1', 'x' and 'z'. Strengths are stored elsewhere.
*
* -- A Note About Names --
* The names of objects are complete, hierarchical names. That is,
* they include the instance name of the module that contains them.
*
* basenames are the name of the object without the containing
* scope. These names are unique within a scope, but not necessarily
* throughout the design.
*/
typedef struct ivl_array_s *ivl_array_t;
typedef struct ivl_delaypath_s*ivl_delaypath_t;
typedef struct ivl_design_s *ivl_design_t;
typedef struct ivl_event_s *ivl_event_t;
typedef struct ivl_expr_s *ivl_expr_t;
typedef struct ivl_lpm_s *ivl_lpm_t;
typedef struct ivl_lval_s *ivl_lval_t;
typedef struct ivl_net_const_s*ivl_net_const_t;
typedef struct ivl_net_logic_s*ivl_net_logic_t;
typedef struct ivl_udp_s *ivl_udp_t;
typedef struct ivl_net_probe_s*ivl_net_probe_t;
typedef struct ivl_nexus_s *ivl_nexus_t;
typedef struct ivl_nexus_ptr_s*ivl_nexus_ptr_t;
typedef struct ivl_parameter_s*ivl_parameter_t;
typedef struct ivl_process_s *ivl_process_t;
typedef struct ivl_scope_s *ivl_scope_t;
typedef struct ivl_signal_s *ivl_signal_t;
typedef struct ivl_memory_s *ivl_memory_t; /* DEPRECATED */
typedef struct ivl_statement_s*ivl_statement_t;
/*
* These are types that are defined as enumerations. These have
* explicit values so that the binary API is a bit more resilient to
* changes and additions to the enumerations.
*/
typedef enum ivl_drive_e {
IVL_DR_HiZ = 0,
IVL_DR_SMALL = 1,
IVL_DR_MEDIUM = 2,
IVL_DR_WEAK = 3,
IVL_DR_LARGE = 4,
IVL_DR_PULL = 5,
IVL_DR_STRONG = 6,
IVL_DR_SUPPLY = 7
} ivl_drive_t;
/* This is the type of an ivl_expr_t object. The explicit numbers
allow additions to the enumeration without causing values to shift
and incompatibilities to be introduced. */
typedef enum ivl_expr_type_e {
IVL_EX_NONE = 0,
IVL_EX_ARRAY = 18,
IVL_EX_BINARY = 2,
IVL_EX_CONCAT = 3,
IVL_EX_EVENT = 17,
IVL_EX_MEMORY = 4,
IVL_EX_NUMBER = 5,
IVL_EX_SCOPE = 6,
IVL_EX_SELECT = 7,
IVL_EX_SFUNC = 8,
IVL_EX_SIGNAL = 9,
IVL_EX_STRING = 10,
IVL_EX_TERNARY = 11,
IVL_EX_UFUNC = 12,
IVL_EX_ULONG = 13,
IVL_EX_UNARY = 14,
IVL_EX_REALNUM = 16
} ivl_expr_type_t;
/* This is the type code for an ivl_net_logic_t object. */
typedef enum ivl_logic_e {
IVL_LO_NONE = 0,
IVL_LO_AND = 1,
IVL_LO_BUF = 2,
IVL_LO_BUFIF0 = 3,
IVL_LO_BUFIF1 = 4,
IVL_LO_BUFZ = 5,
IVL_LO_NAND = 6,
IVL_LO_NMOS = 7,
IVL_LO_NOR = 8,
IVL_LO_NOT = 9,
IVL_LO_NOTIF0 = 10,
IVL_LO_NOTIF1 = 11,
IVL_LO_OR = 12,
IVL_LO_PULLDOWN = 13,
IVL_LO_PULLUP = 14,
IVL_LO_RNMOS = 15,
IVL_LO_RPMOS = 16,
IVL_LO_PMOS = 17,
IVL_LO_XNOR = 18,
IVL_LO_XOR = 19,
IVL_LO_UDP = 21
} ivl_logic_t;
/* This is the type of an LPM object. */
typedef enum ivl_lpm_type_e {
IVL_LPM_ADD = 0,
IVL_LPM_ARRAY = 30,
IVL_LPM_CONCAT = 16,
IVL_LPM_CMP_EEQ= 18, /* Case EQ (===) */
IVL_LPM_CMP_EQ = 10,
IVL_LPM_CMP_GE = 1,
IVL_LPM_CMP_GT = 2,
IVL_LPM_CMP_NE = 11,
IVL_LPM_CMP_NEE= 19, /* Case NE (!==) */
IVL_LPM_DIVIDE = 12,
IVL_LPM_FF = 3,
IVL_LPM_MOD = 13,
IVL_LPM_MULT = 4,
IVL_LPM_MUX = 5,
IVL_LPM_PART_BI= 28, /* part select: bi-directional (part on 0) */
IVL_LPM_PART_VP= 15, /* part select: vector to part */
IVL_LPM_PART_PV= 17, /* part select: part written to vector */
IVL_LPM_RE_AND = 20,
IVL_LPM_RE_NAND= 21,
IVL_LPM_RE_NOR = 22,
IVL_LPM_RE_OR = 23,
IVL_LPM_RE_XNOR= 24,
IVL_LPM_RE_XOR = 25,
IVL_LPM_REPEAT = 26,
IVL_LPM_SFUNC = 29,
IVL_LPM_SHIFTL = 6,
IVL_LPM_SHIFTR = 7,
IVL_LPM_SIGN_EXT=27,
IVL_LPM_SUB = 8,
/* IVL_LPM_RAM = 9, / obsolete */
IVL_LPM_UFUNC = 14
} ivl_lpm_type_t;
/* The path edge type is the edge type used to select a specific
delay. */
typedef enum ivl_path_edge_e {
IVL_PE_01 = 0, IVL_PE_10, IVL_PE_0z,
IVL_PE_z1, IVL_PE_1z, IVL_PE_z0,
IVL_PE_0x, IVL_PE_x1, IVL_PE_1x,
IVL_PE_x0, IVL_PE_xz, IVL_PE_zx,
IVL_PE_COUNT
} ivl_path_edge_t;
/* Processes are initial or always blocks with a statement. This is
the type of the ivl_process_t object. */
typedef enum ivl_process_type_e {
IVL_PR_INITIAL = 0,
IVL_PR_ALWAYS = 1
} ivl_process_type_t;
/* These are the sorts of reasons a scope may come to be. These types
are properties of ivl_scope_t objects. */
typedef enum ivl_scope_type_e {
IVL_SCT_MODULE = 0,
IVL_SCT_FUNCTION= 1,
IVL_SCT_TASK = 2,
IVL_SCT_BEGIN = 3,
IVL_SCT_FORK = 4,
IVL_SCT_GENERATE= 5
} ivl_scope_type_t;
/* Signals (ivl_signal_t) that are ports into the scope that contains
them have a port type. Otherwise, they are port IVL_SIP_NONE. */
typedef enum ivl_signal_port_e {
IVL_SIP_NONE = 0,
IVL_SIP_INPUT = 1,
IVL_SIP_OUTPUT= 2,
IVL_SIP_INOUT = 3
} ivl_signal_port_t;
/* This is the type code for an ivl_signal_t object. Implicit types
are resolved by the core compiler, and integers are converted into
signed registers. */
typedef enum ivl_signal_type_e {
IVL_SIT_NONE = 0,
IVL_SIT_REG = 1,
IVL_SIT_TRI = 4,
IVL_SIT_TRI0 = 5,
IVL_SIT_TRI1 = 6,
IVL_SIT_TRIAND = 7,
IVL_SIT_TRIOR = 8
} ivl_signal_type_t;
/* This is the type code for ivl_statement_t objects. */
typedef enum ivl_statement_type_e {
IVL_ST_NONE = 0,
IVL_ST_NOOP = 1,
IVL_ST_ASSIGN = 2,
IVL_ST_ASSIGN_NB = 3,
IVL_ST_BLOCK = 4,
IVL_ST_CASE = 5,
IVL_ST_CASER = 24, /* Case statement with real expressions. */
IVL_ST_CASEX = 6,
IVL_ST_CASEZ = 7,
IVL_ST_CASSIGN = 8,
IVL_ST_CONDIT = 9,
IVL_ST_DEASSIGN = 10,
IVL_ST_DELAY = 11,
IVL_ST_DELAYX = 12,
IVL_ST_DISABLE = 13,
IVL_ST_FORCE = 14,
IVL_ST_FOREVER = 15,
IVL_ST_FORK = 16,
IVL_ST_RELEASE = 17,
IVL_ST_REPEAT = 18,
IVL_ST_STASK = 19,
IVL_ST_TRIGGER = 20,
IVL_ST_UTASK = 21,
IVL_ST_WAIT = 22,
IVL_ST_WHILE = 23
} ivl_statement_type_t;
/* This is the type of a variable, and also used as the type for an
expression. */
typedef enum ivl_variable_type_e {
IVL_VT_VOID = 0, /* Not used */
IVL_VT_NO_TYPE = 1, /* Place holder for missing/unknown type. */
IVL_VT_REAL = 2,
IVL_VT_BOOL = 3,
IVL_VT_LOGIC = 4,
IVL_VT_VECTOR = IVL_VT_LOGIC /* For compatibility */
} ivl_variable_type_t;
/* This is the type of the function to apply to a process. */
typedef int (*ivl_process_f)(ivl_process_t net, void*cd);
/* This is the type of a function to apply to a scope. The ivl_scope_t
parameter is the scope, and the cd parameter is client data that
the user passes to the scanner. */
typedef int (ivl_scope_f)(ivl_scope_t net, void*cd);
/* Attributes, which can be attached to various object types, have
this form. */
typedef enum ivl_attribute_type_e {
IVL_ATT_VOID = 0,
IVL_ATT_STR,
IVL_ATT_NUM
} ivl_attribute_type_t;
struct ivl_attribute_s {
const char*key;
ivl_attribute_type_t type;
union val_ {
const char*str;
long num;
} val;
};
typedef const struct ivl_attribute_s*ivl_attribute_t;
/* DELAYPATH
* Delaypath objects represent delay paths called out by a specify
* block in the verilog source file. The destination signal references
* the path object, which in turn points to the source for the path.
*
* ivl_path_source
* This returns the nexus that is the source end of the delay
* path. Transitions on the source are the start of the delay time
* for this path.
*/
extern ivl_nexus_t ivl_path_source(ivl_delaypath_t obj);
extern uint64_t ivl_path_delay(ivl_delaypath_t obj, ivl_path_edge_t pt);
/* DESIGN
* When handed a design (ivl_design_t) there are a few things that you
* can do with it. The Verilog program has one design that carries the
* entire program. Use the design methods to iterate over the elements
* of the design.
*
* ivl_design_flag
* This function returns the string value of a named flag. Flags
* come from the "-fkey=value" options to the iverilog command and
* are stored in a map for this function. Given the key, this
* function returns the value.
*
* The special key "-o" is the argument to the -o flag of the
* command line (or the default if the -o flag is not used) and is
* generally how the target learns the name of the output file.
*
* ivl_design_process
* This function scans the processes (threads) in the design. It
* calls the user supplied function on each of the processes until
* one of the functors returns non-0 or all the processes are
* scanned. This function will return 0, or the non-zero value that
* was returned from the last scanned process.
*
* ivl_design_root (ANACHRONISM)
* A design has a root named scope that is an instance of the top
* level module in the design. This is a hook for naming the
* design, or for starting the scope scan.
*
* ivl_design_roots
* A design has some number of root scopes. These are the starting
* points for structural elaboration. This function returns to the
* caller a pointer to an ivl_scope_t array, and the size of the
* array.
*
* ivl_design_time_precision
* A design as a time precision. This is the size in seconds (a
* signed power of 10) of a simulation tick.
*/
extern const char* ivl_design_flag(ivl_design_t des, const char*key);
extern int ivl_design_process(ivl_design_t des,
ivl_process_f fun, void*cd);
extern ivl_scope_t ivl_design_root(ivl_design_t des);
extern void ivl_design_roots(ivl_design_t des,
ivl_scope_t **scopes,
unsigned int *nscopes);
extern int ivl_design_time_precision(ivl_design_t des);
extern unsigned ivl_design_consts(ivl_design_t des);
extern ivl_net_const_t ivl_design_const(ivl_design_t, unsigned idx);
/* LITERAL CONSTANTS
* Literal constants are nodes with no input and a single constant
* output. The form of the output depends on the type of the node.
* The output is an array of 4-value bits, using a single char
* value for each bit. The bits of the vector are in canonical (lsb
* first) order for the width of the constant.
*
* ivl_const_type
* The is the type of the node.
*
* ivl_const_bits
* This returns a pointer to an array of conststant characters,
* each byte a '0', '1', 'x' or 'z'. The array is *not* nul
* terminated.
*
* ivl_const_nex
* Return the ivl_nexus_t of the output for the constant.
*
* ivl_const_signed
* Return true (!0) if the constant is a signed value, 0 otherwise.
*
* ivl_const_width
* Return the width, in logical bits, of the constant.
*
* SEMANTIC NOTES
*
* The const_type of the literal constant must match the
* ivl_signal_data_type if the signals that share the nexus of this
* node. The compiler makes sure it is so, converting constant values
* as needed.
*
* - IVL_VT_LOGIC
*
* - IVL_VT_REAL
* Real valued constants have a width of 1. The value emitted to the
* output is ivl_const_real.
*/
extern ivl_variable_type_t ivl_const_type(ivl_net_const_t net);
extern const char* ivl_const_bits(ivl_net_const_t net);
extern ivl_nexus_t ivl_const_nex(ivl_net_const_t net);
extern int ivl_const_signed(ivl_net_const_t net);
extern unsigned ivl_const_width(ivl_net_const_t net);
extern double ivl_const_real(ivl_net_const_t net);
/* extern ivl_nexus_t ivl_const_pin(ivl_net_const_t net, unsigned idx); */
/* extern unsigned ivl_const_pins(ivl_net_const_t net); */
/* EVENTS
*
* Events are a unification of named events and implicit events
* generated by the @ statements.
*
* FUNCTION SUMMARY
*
* ivl_event_name (Obsolete)
* ivl_event_basename
* Return the name of the event. The basename is the name within
* the scope, as declared by the user or generated by elaboration.
*
* ivl_event_scope
* All events exist within a scope.
*
* SEMANTICS NOTES
*
* Named events (i.e. event objects declared by the Verilog
* declaration "event foo") are recognized by the fact that they have
* no edge sources. The name of the event as given in the Verilog
* source is available from the ivl_event_basename function.
*
* Named events are referenced in trigger statements.
*
* Edge events are created implicitly by the @(...) Verilog syntax to
* watch for the correct type of edge for the functor being
* watched. The nodes to watch are collected into groups based on the
* type of edge to be watched for on that node. For example, nodes to
* be watched for positive edges are accessed via the ivl_event_npos
* and ivl_event_pos functions.
*/
extern const char* ivl_event_name(ivl_event_t net);
extern const char* ivl_event_basename(ivl_event_t net);
extern ivl_scope_t ivl_event_scope(ivl_event_t net);
extern unsigned ivl_event_nany(ivl_event_t net);
extern ivl_nexus_t ivl_event_any(ivl_event_t net, unsigned idx);
extern unsigned ivl_event_nneg(ivl_event_t net);
extern ivl_nexus_t ivl_event_neg(ivl_event_t net, unsigned idx);
extern unsigned ivl_event_npos(ivl_event_t net);
extern ivl_nexus_t ivl_event_pos(ivl_event_t net, unsigned idx);
/* EXPRESSIONS
*
* These methods operate on expression objects from the
* design. Expressions mainly exist in behavioral code. The
* ivl_expr_type() function returns the type of the expression node,
* and the remaining functions access value bits of the expression.
*
* ivl_expr_signed
* This method returns true (!= 0) if the expression node
* represents a signed expression. It is possible for sub-
* expressions to be unsigned even if a node is signed, but the
* IVL core figures all this out for you. At any rate, this method
* can be applied to any expression node.
*
* ivl_expr_type
* Get the type of the expression node. Every expression node has a
* type, which can affect how some of the other expression methods
* operate on the node
*
* ivl_expr_value
* Get the data type of the expression node. This uses the variable
* type enum to express the type of the expression node.
*
* ivl_expr_width
* This method returns the bit width of the expression at this
* node. It can be applied to any expression node, and returns the
* *output* width of the expression node.
*
* ivl_expr_parameter
* This function returns the ivl_parameter_t object that represents
* this object, or 0 (nil) if it is not a parameter value. This
* function allows the code generator to detect the case where the
* expression is a parameter. This will normally only return a
* non-nil value for constants.
*
* ivl_expr_opcode
* IVL_EX_BINARY and IVL_EX_UNARY expression nodes include an
* opcode from this table:
* & -- AND
* A -- NAND (~&)
* X -- XNOR (~^)
* * -- Multiply
*
* SEMANTIC NOTES
*
* - IVL_EX_ARRAY
* This expression type is a special case of the IVL_EX_SIGNAL where
* the target is an array (ivl_signal_t with an array_count) but there
* is no index expression. This is used only in the special situation
* where the array is passed to a system task/function. The function
* ivl_expr_signal returns the ivl_signal_t of the array object, and
* from that all the properties of the array can be determined.
*
* - IVL_EX_BINARY
*
* - IVL_EX_SELECT
* This expression takes two operands, oper1 is the expression to
* select from, and oper2 is the selection base. The ivl_expr_width
* value is the width of the bit/part select. The ivl_expr_oper1 value
* is the base of a vector. The compiler has already figured out any
* conversion from signal units to vector units, so the result of
* ivl_expr_oper1 should range from 0 to ivl_expr_width().
*
* - IVL_EX_SIGNAL
* This expression references a signal vector. The ivl_expr_signal
* function gets a handle for the signal that is referenced. The
* signal may be an array (see the ivl_signal_array_count function)
* that is addressed by the expression returned by the ivl_expr_oper1
* function. This expression returns a *canonical* address. The core
* compiler already corrected the expression to account for index
* bases.
*
* The ivl_expr_width function returns the vector width of the signal
* word. The ivl_expr_value returns the data type of the word.
*
* Bit and part selects are not done here. The IVL_EX_SELECT
* expression does bit/part selects on the word read from the signal.
*/
extern ivl_expr_type_t ivl_expr_type(ivl_expr_t net);
extern ivl_variable_type_t ivl_expr_value(ivl_expr_t net);
/* IVL_EX_NUMBER */
extern const char* ivl_expr_bits(ivl_expr_t net);
/* IVL_EX_UFUNC */
extern ivl_scope_t ivl_expr_def(ivl_expr_t net);
/* IVL_EX_REALNUM */
extern double ivl_expr_dvalue(ivl_expr_t net);
/* IVL_EX_SIGNAL, IVL_EX_SFUNC, IVL_EX_VARIABLE */
extern const char* ivl_expr_name(ivl_expr_t net);
/* IVL_EX_BINARY IVL_EX_UNARY */
extern char ivl_expr_opcode(ivl_expr_t net);
/* IVL_EX_BINARY IVL_EX_UNARY, IVL_EX_MEMORY IVL_EX_TERNARY */
extern ivl_expr_t ivl_expr_oper1(ivl_expr_t net);
/* IVL_EX_BINARY IVL_EX_TERNARY */
extern ivl_expr_t ivl_expr_oper2(ivl_expr_t net);
/* IVL_EX_TERNARY */
extern ivl_expr_t ivl_expr_oper3(ivl_expr_t net);
/* and expression */
extern ivl_parameter_t ivl_expr_parameter(ivl_expr_t net);
/* IVL_EX_CONCAT IVL_EX_UFUNC */
extern ivl_expr_t ivl_expr_parm(ivl_expr_t net, unsigned idx);
/* IVL_EX_CONCAT IVL_EX_SFUNC IVL_EX_UFUNC */
extern unsigned ivl_expr_parms(ivl_expr_t net);
/* IVL_EX_CONCAT */
extern unsigned ivl_expr_repeat(ivl_expr_t net);
/* IVL_EX_EVENT */
extern ivl_event_t ivl_expr_event(ivl_expr_t net);
/* IVL_EX_SCOPE */
extern ivl_scope_t ivl_expr_scope(ivl_expr_t net);
/* IVL_EX_SIGNAL */
extern ivl_signal_t ivl_expr_signal(ivl_expr_t net);
/* any expression */
extern int ivl_expr_signed(ivl_expr_t net);
/* IVL_EX_STRING */
extern const char* ivl_expr_string(ivl_expr_t net);
/* IVL_EX_ULONG */
extern unsigned long ivl_expr_uvalue(ivl_expr_t net);
/* any expression */
extern unsigned ivl_expr_width(ivl_expr_t net);
/* LOGIC
* These types and functions support manipulation of logic gates. The
* ivl_logic_t enumeration identifies the various kinds of gates that
* the ivl_net_logic_t can represent. The various functions then
* provide access to the bits of information for a given logic device.
*
* The ivl_net_logic_t nodes are bit-slice devices. That means that
* the device may have width (and therefore processes vectors) but
* each bit slice of the width is independent.
*
* ivl_logic_type
* This method returns the type of logic gate that the node
* represents. The logic type implies the meaning of the various pins.
*
* ivl_logic_name (obsolete)
* This method returns the complete name of the logic gate. Every
* gate has a complete name (that includes the scope) even if the
* Verilog source doesn't include one. The compiler will choose one
* if necessary.
*
* ivl_logic_basename
* This is the name of the gate without the scope part.
*
* ivl_logic_scope
* This is the scope that directly contains the logic device.
*
* ivl_logic_pins
* ivl_logic_pin
* Return the nexus for the pin. If two pins are connected
* together, then these values are the same. Use the nexus
* functions to find other pins that are connected to this nexus.
*
* ivl_logic_width
* This returns the width of the logic array. This does not affect
* the number of pins, but implies the width of the vector at each
* pin.
*
* ivl_logic_delay
* Logic devices have a delay for each transition (0, 1 and Z).
*
* ivl_logic_attr (obsolete)
* Return the value of a specific attribute, given the key name as
* a string. If the key is not defined, then return 0 (null).
*
* ivl_logic_attr_cnt
* ivl_logic_attr_val
* These support iterating over logic attributes. The _cnt method
* returns the number of attributes attached to the gate, and the
* ivl_logic_attr_val returns the value of the attribute.
*
* SEMANTIC NOTES
* The ivl_logic_width applies to all the pins of a logic device. If a
* logic device has width, that means that it is actually an array of
* logic devices tha each process a bit slice of the
* inputs/output. That implies that the widths of all the inputs and
* the output must be identical.
*
* The ivl_logic_width and ivl_logic_pins are *not* related. A logic
* device has a number of pins that is the number of inputs to a logic
* array of identical gates, and the ivl_logic_width, is the width of
* the vector into each input pin and out of the output pin.
*
* The output pin is pin-0. The ivl_logic_driveX functions return the
* drive strengths for the output pin-0, and match the drive values
* stored in the ivl_nexus_ptr_t object for the pin.
*
* Logic devices have a logic propagation delay. The delay can be any
* expression, although the most common expression is an IVL_EX_NUMBER
* for a number value. The expression already includes scaling for the
* containing module, so the delay value is always taken to be in
* simulation clock ticks.
*
* If the delay is present, then ivl_logic_delay returns a non-nil
* object. If any of the three delays is present, then all three are
* present, even if they are all the same. The compiler will translate
* shorthands into a complete set of delay expressions.
*
* The ivl_logic_delay expression will always be an IVL_EX_NUMBER, an
* IVL_EX_ULONG, or an IVL_EX_SIGNAL. These expressions can easily be
* used in structural contexts. The compiler will take care of
* elaborating more complex expressions to nets.
*
* - IVL_LO_PULLUP/IVL_LO_PULLDOWN
* These devices are grouped as logic devices with zero inputs because
* the outputs have the same characteristics as other logic
* devices. They are special only in that they have zero inputs, and
* their drivers typically have strength other then strong.
*
* - IVL_LO_UDP
* User defined primitives (UDPs) are like any other logic devices, in
* that they are bit-slice devices. If they have a width, then they
* are repeated to accommodate that width, and that implies that the
* output and all the inputs must have the same width.
*
* The IVL_LO_UDP represents instantiations of UDP devices. The
* ivl_udp_t describes the implementation.
*/
extern const char* ivl_logic_name(ivl_net_logic_t net);
extern const char* ivl_logic_basename(ivl_net_logic_t net);
extern ivl_scope_t ivl_logic_scope(ivl_net_logic_t net);
extern ivl_logic_t ivl_logic_type(ivl_net_logic_t net);
extern ivl_nexus_t ivl_logic_pin(ivl_net_logic_t net, unsigned pin);
extern unsigned ivl_logic_pins(ivl_net_logic_t net);
extern ivl_udp_t ivl_logic_udp(ivl_net_logic_t net);
extern ivl_expr_t ivl_logic_delay(ivl_net_logic_t net, unsigned transition);
extern ivl_drive_t ivl_logic_drive0(ivl_net_logic_t net);
extern ivl_drive_t ivl_logic_drive1(ivl_net_logic_t net);
extern unsigned ivl_logic_width(ivl_net_logic_t net);
/* DEPRECATED */
extern const char* ivl_logic_attr(ivl_net_logic_t net, const char*key);
extern unsigned ivl_logic_attr_cnt(ivl_net_logic_t net);
extern ivl_attribute_t ivl_logic_attr_val(ivl_net_logic_t net, unsigned idx);
/* UDP
* These methods allow access to the ivl_udp_t definition of a UDP.
* The UDP definition is accessed through the ivl_logic_udp method of
* an ivl_net_logic_t object.
*
* ivl_udp_name
* This returns the name of the definition of the primitive.
*
* ivl_udp_nin
* This is the number of inputs for the UDP definition.
*
* ivl_udp_rows
* ivl_udp_row
* These methods give access to the rows that define the table of
* the primitive.
*
* SEMANTIC NOTES
*
* - Combinational primitives
* These devices have no edge dependencies, and have no table entry
* for the current input value. These have ivl_udp_sequ return 0
* (false) and the length of each row is the number of inputs plus 1.
* The first N characters correspond to the N inputs of the
* device. The next character, the last character, is the output for
* that row.
*
* - Sequential primitives
* These devices allow edge transitions, and the rows are 1+N+1
* characters long. The first character is the current output, the
* next N characters the current input and the last character is the
* new output.
*
* The ivl_udp_init value is only valid if the device is
* sequential. It is the initial value for the output of the storage
* element.
*/
extern int ivl_udp_sequ(ivl_udp_t net);
extern unsigned ivl_udp_nin(ivl_udp_t net);
extern unsigned ivl_udp_init(ivl_udp_t net);
extern const char* ivl_udp_row(ivl_udp_t net, unsigned idx);
extern unsigned ivl_udp_rows(ivl_udp_t net);
extern const char* ivl_udp_name(ivl_udp_t net);
/* LPM
* These functions support access to the properties of LPM
* devices. LPM devices are a variety of devices that handle more
* complex structural semantics. They are based on EIA LPM standard
* devices, but vary to suite the technical situation.
*
* These are the functions that apply to all LPM devices:
*
* ivl_lpm_name (Obsolete)
* ivl_lpm_basename
* Return the name of the device. The name is the name of the
* device with the scope part, and the basename is without the scope.
*
* ivl_lpm_scope
* LPM devices exist within a scope. Return the scope that contains
* this device.
*
* ivl_lpm_type
* Return the ivl_lpm_type_t of the specific LPM device.
*
* ivl_lpm_width
* Return the width of the LPM device. What this means depends on
* the LPM type, but it generally has to do with the width of the
* output data path.
*
*
* These functions apply to a subset of the LPM devices, or may have
* varying meaning depending on the device:
*
* ivl_lpm_base
* The IVL_LPM_PART objects use this value as the base (first bit)
* of the part select. The ivl_lpm_width is the size of the part.
*
* ivl_lpm_data
* Return the input data nexus for device types that have input
* vectors. The "idx" parameter selects which data input is selected.
*
* ivl_lpm_datab (ANACHRONISM)
* This is the same as ivl_lpm_data(net,1), in other words the
* second data input. Use the ivl_lpm_data method instead.
*
* ivl_lpm_q
* Return the output data nexus for device types that have a single
* output vector. This is most devices, it turns out.
*
* ivl_lpm_selects
* This is the size of the select input for a LPM_MUX device, or the
* address bus width of an LPM_RAM.
*
* ivl_lpm_signed
* Arithmetic LPM devices may be signed or unsigned if there is a
* distinction. For some devices this gives the signedness of the
* output, but not all devices.
*
* ivl_lpm_size
* In addition to a width, some devices have a size. The size is
* often the number of inputs per out, i.e., the number of inputs
* per bit for a MUX.
*
* SEMANTIC NOTES
*
* - Concatenation (IVL_LPM_CONCAT)
* These devices take vectors in and combine them to form a single
* output the width specified by ivl_lpm_width.
*
* The ivl_lpm_q nexus is the output from the concatenation.
*
* The ivl_lpm_data function returns the connections for the inputs to
* the concatentation. The ivl_lpm_size function returns the number of
* inputs help by the device.
*
* - Divide (IVL_LPM_DIVIDE)
* The divide operators take two inputs and generate an output. The
* ivl_lpm_width returns the width of the result. The width of the
* inputs are their own.
*
* - Multiply (IVL_LPM_MULT)
* The multiply takes two inputs and generates an output. Unlike other
* arithmetic nodes, the width only refers to the output. The inputs
* have independent widths, to reflect the arithmetic truth that the
* width of a general multiply is the sum of the widths of the
* inputs. In fact, the compiler doesn't assure that the widths of the
* inputs add up to the width of the output, but the possibility
* exists. It is *not* an error for the sum of the input widths to be
* more then the width of the output, although the possibility of
* overflow exists at run time.
*
* Multiply may be signed. If so, the output should be sign extended
* to fill in its result.
*
* - Part Select (IVL_LPM_PART_VP and IVL_LPM_PART_PV)
* There are two part select devices, one that extracts a part from a
* vector, and another that writes a part of a vector. The _VP is
* Vector-to-Part, and _PV is Part-to-Vector. The _VP form is meant to
* model part/bin selects in r-value expressions, where the _PV from
* is meant to model part selects in l-value nets.
*
* In both cases, ivl_lpm_data(0) is the input pin, and ivl_lpm_q is the
* output. In the case of the _VP device, the vector is input and the
* part is the output. In the case of the _PV device, the part is the
* input and the vector is the output.
*
* If the base of the part select is non-constant, then
* ivl_lpm_data(1) is non-nil and is the select, or base, address of
* the part. If this pin is nil, then the constant base is used
* instead.
*
* Also in both cases, the width of the device is the width of the
* part. In the _VP case, this is obvious as the output nexus has the
* part width. In the _PV case, this is a little less obvious, but
* still correct. The output being written to the wider vector is
* indeed the width of the part, even though it is written to a wider
* gate. The target will need to handle this case specially.
*
* - Bi-directional Part Select (IVL_LPM_PART_BI)
* This is not exactly a part select but a bi-directional partial link
* of two nexa with different widths. This is used to implement tran
* devices and inout ports in certain cases. The device width is the
* width of the part. The ivl_lpm_q is the part end, and the
* ivl_lpm_data(0) is the non-part end.
*
* - Comparisons (IVL_LPM_CMP_GT/GE/EQ/NE/EEQ/NEE)
* These devices have two inputs, available by the ivl_lpm_data()
* function, and one output available by the ivl_lpm_q function. The
* output width is always 1, but the ivl_lpm_width() returns the width
* of the inputs. Both inputs must have the same width.
*
* The CMP_GE and CMP_GT nodes may also be signed or unsigned, with
* the obvious implications. The widths are matched by the compiler
* (so the target need not worry about sign extension) but when doing
* magnitude compare, the signedness does matter. In any case, the
* result of the compare is always unsigned.
*
* - Mux Device (IVL_LPM_MUX)
* The MUX device has a q output, a select input, and a number of data
* inputs. The ivl_lpm_q output and the ivl_lpm_data inputs all have
* the width from the ivl_lpm_width() method. The Select input, from
* ivl_lpm_select, has the width ivl_lpm_selects().
*
* The ivl_lpm_data() method returns the inputs of the MUX device. The
* ivl_lpm_size() method returns the number of data inputs there
* are. All the data inputs have the same width, the width of the
* ivl_lpm_q output. The type of the device is devined from the
* inputs and the Q. All the types must be exactly the same.
*
* - D-FlipFlop (IVL_LPM_FF)
* This data is an edge sensitive register. The ivl_lpm_q output and
* single ivl_lpm_data input are the same with, ivl_lpm_width. This
* device carries a vector like other LPM devices.
*
* - Memory port (IVL_LPM_RAM) (deprecated in favor of IVL_LPM_ARRAY)
* These are structural ports into a memory device. They represent
* address/data ports of a memory device that the context can hook to
* for read or write. Read devices have an ivl_lpm_q output port that
* is the data being read.
*
* The ivl_lpm_memory function returns the ivl_memory_t for the memory
* that the port access. The ivl_lpm_width for the port then must
* match the ivl_memory_width of the memory device.
*
* Read or write, the ivl_lpm_select nexus is the address. The
* ivl_lpm_selects function returns the vector width of the
* address. The range of the address is always from 0 to the memory
* size-1 -- the canonical form. It is up to the compiler to generate
* offsets to correct for a range declaration.
*
* Read ports use the ivl_lpm_q as the data output, and write ports
* use the ivl_lpm_data(0) as the input. In either case the width of
* the vector matches the width of the memory itself.
*
* - Reduction operators (IVL_LPM_RE_*)
* These devices have one input, a vector, and generate a single bit
* result. The width from the ivl_lpm_width is the width of the input
* vector.
*
* - Repeat Node (IVL_LPM_REPEAT)
* This node takes as input a single vector, and outputs a single
* vector. The ivl_lpm_width if this node is the width of the *output*
* vector. The ivl_lpm_size() returns the number of times the input is