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elaborate.cc
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/*
* Copyright (c) 1998-2002 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: elaborate.cc,v 1.266 2002/12/05 04:15:14 steve Exp $"
#endif
# include "config.h"
/*
* Elaboration takes as input a complete parse tree and the name of a
* root module, and generates as output the elaborated design. This
* elaborated design is presented as a Module, which does not
* reference any other modules. It is entirely self contained.
*/
# include <typeinfo>
# include <strstream>
# include <list>
# include "pform.h"
# include "PEvent.h"
# include "netlist.h"
# include "netmisc.h"
# include "util.h"
# include "parse_api.h"
# include "compiler.h"
static Link::strength_t drive_type(PGate::strength_t drv)
{
switch (drv) {
case PGate::HIGHZ:
return Link::HIGHZ;
case PGate::WEAK:
return Link::WEAK;
case PGate::PULL:
return Link::PULL;
case PGate::STRONG:
return Link::STRONG;
case PGate::SUPPLY:
return Link::SUPPLY;
default:
assert(0);
}
return Link::STRONG;
}
void PGate::elaborate(Design*des, NetScope*scope) const
{
cerr << "internal error: what kind of gate? " <<
typeid(*this).name() << endl;
}
/*
* Elaborate the continuous assign. (This is *not* the procedural
* assign.) Elaborate the lvalue and rvalue, and do the assignment.
*/
void PGAssign::elaborate(Design*des, NetScope*scope) const
{
assert(scope);
unsigned long rise_time, fall_time, decay_time;
eval_delays(des, scope, rise_time, fall_time, decay_time);
Link::strength_t drive0 = drive_type(strength0());
Link::strength_t drive1 = drive_type(strength1());
assert(pin(0));
assert(pin(1));
/* Elaborate the l-value. */
NetNet*lval = pin(0)->elaborate_lnet(des, scope);
if (lval == 0) {
des->errors += 1;
return;
}
/* Handle the special case that the rval is simply an
identifier. Get the rval as a NetNet, then use NetBUFZ
objects to connect it to the l-value. This is necessary to
direct drivers. This is how I attach strengths to the
assignment operation. */
if (const PEIdent*id = dynamic_cast<const PEIdent*>(pin(1))) {
NetNet*rid = id->elaborate_net(des, scope, lval->pin_count(),
0, 0, 0, Link::STRONG,
Link::STRONG);
if (rid == 0) {
des->errors += 1;
return;
}
assert(rid);
/* If the right hand net is the same type as the left
side net (i.e. WIRE/WIRE) then it is enough to just
connect them together. Otherwise, put a bufz between
them to carry strengths from the rval.
While we are at it, handle the case where the r-value
is not as wide as th l-value by padding with a
constant-0. */
unsigned cnt = lval->pin_count();
if (rid->pin_count() < cnt)
cnt = rid->pin_count();
bool need_driver_flag = false;
/* If the device is linked to itself, a driver is
needed. Should I print a warning here? */
for (unsigned idx = 0 ; idx < cnt ; idx += 1) {
if (lval->pin(idx) .is_linked (rid->pin(idx))) {
need_driver_flag = true;
break;
}
}
/* If the nets are different type (i.e. reg vs tri) then
a driver is needed. */
if (rid->type() != lval->type())
need_driver_flag = true;
/* If there is a delay, then I need a driver to carry
it. */
if (rise_time || fall_time || decay_time)
need_driver_flag = true;
/* If there is a strength to be carried, then I need a
driver to carry that strength. */
for (unsigned idx = 0 ; idx < cnt ; idx += 1) {
if (rid->pin(idx).drive0() != drive0) {
need_driver_flag = true;
break;
}
if (rid->pin(idx).drive1() != drive1) {
need_driver_flag = true;
break;
}
}
if (! need_driver_flag) {
/* Don't need a driver, presumably because the
r-value already has the needed drivers. Just
hook things up. */
unsigned idx;
for (idx = 0 ; idx < cnt; idx += 1)
connect(lval->pin(idx), rid->pin(idx));
if (cnt < lval->pin_count()) {
verinum tmpv (0UL, lval->pin_count()-cnt);
NetConst*tmp = new NetConst(scope,
scope->local_hsymbol(),
tmpv);
des->add_node(tmp);
for (idx = cnt ; idx < lval->pin_count() ; idx += 1)
connect(lval->pin(idx), tmp->pin(idx-cnt));
}
} else {
/* Do need a driver. Use BUFZ objects to carry the
strength and delays. */
unsigned idx;
for (idx = 0 ; idx < cnt ; idx += 1) {
NetBUFZ*dev = new NetBUFZ(scope,
scope->local_hsymbol());
connect(lval->pin(idx), dev->pin(0));
connect(rid->pin(idx), dev->pin(1));
dev->rise_time(rise_time);
dev->fall_time(fall_time);
dev->decay_time(decay_time);
dev->pin(0).drive0(drive0);
dev->pin(0).drive1(drive1);
des->add_node(dev);
}
if (cnt < lval->pin_count()) {
NetConst*dev = new NetConst(scope,
scope->local_hsymbol(),
verinum::V0);
des->add_node(dev);
dev->pin(0).drive0(drive0);
dev->pin(0).drive1(drive1);
for (idx = cnt ; idx < lval->pin_count() ; idx += 1)
connect(lval->pin(idx), dev->pin(0));
}
}
return;
}
/* Elaborate the r-value. Account for the initial decays,
which are going to be attached to the last gate before the
generated NetNet. */
NetNet*rval = pin(1)->elaborate_net(des, scope,
lval->pin_count(),
rise_time, fall_time, decay_time,
drive0, drive1);
if (rval == 0) {
cerr << get_line() << ": error: Unable to elaborate r-value: "
<< *pin(1) << endl;
des->errors += 1;
return;
}
assert(lval && rval);
/* If the r-value insists on being smaller then the l-value
(perhaps it is explicitly sized) the pad it out to be the
right width so that something is connected to all the bits
of the l-value. */
if (lval->pin_count() > rval->pin_count())
rval = pad_to_width(des, rval, lval->pin_count());
for (unsigned idx = 0 ; idx < lval->pin_count() ; idx += 1)
connect(lval->pin(idx), rval->pin(idx));
if (lval->local_flag())
delete lval;
}
/*
* Elaborate a Builtin gate. These normally get translated into
* NetLogic nodes that reflect the particular logic function.
*/
void PGBuiltin::elaborate(Design*des, NetScope*scope) const
{
unsigned count = 1;
unsigned low = 0, high = 0;
string name = get_name();
if (name == "")
name = scope->local_hsymbol();
else
name = scope->name()+"."+name;
/* If the verilog source has a range specification for the
gates, then I am expected to make more then one
gate. Figure out how many are desired. */
if (msb_) {
verinum*msb = msb_->eval_const(des, scope);
verinum*lsb = lsb_->eval_const(des, scope);
if (msb == 0) {
cerr << get_line() << ": error: Unable to evaluate "
"expression " << *msb_ << endl;
des->errors += 1;
return;
}
if (lsb == 0) {
cerr << get_line() << ": error: Unable to evaluate "
"expression " << *lsb_ << endl;
des->errors += 1;
return;
}
if (msb->as_long() > lsb->as_long())
count = msb->as_long() - lsb->as_long() + 1;
else
count = lsb->as_long() - msb->as_long() + 1;
low = lsb->as_long();
high = msb->as_long();
}
/* Allocate all the getlist nodes for the gates. */
NetLogic**cur = new NetLogic*[count];
assert(cur);
/* Calculate the gate delays from the delay expressions
given in the source. For logic gates, the decay time
is meaningless because it can never go to high
impedence. However, the bufif devices can generate
'bz output, so we will pretend that anything can.
If only one delay value expression is given (i.e. #5
nand(foo,...)) then rise, fall and decay times are
all the same value. If two values are given, rise and
fall times are use, and the decay time is the minimum
of the rise and fall times. Finally, if all three
values are given, they are taken as specified. */
unsigned long rise_time, fall_time, decay_time;
eval_delays(des, scope, rise_time, fall_time, decay_time);
struct attrib_list_t*attrib_list = 0;
unsigned attrib_list_n = 0;
attrib_list = evaluate_attributes(attributes, attrib_list_n,
des, scope);
/* Now make as many gates as the bit count dictates. Give each
a unique name, and set the delay times. */
for (unsigned idx = 0 ; idx < count ; idx += 1) {
strstream tmp;
unsigned index;
if (low < high)
index = low + idx;
else
index = low - idx;
tmp << name << "<" << index << ">" << ends;
const string inm = tmp.str();
switch (type()) {
case AND:
cur[idx] = new NetLogic(scope, inm, pin_count(),
NetLogic::AND);
break;
case BUF:
cur[idx] = new NetLogic(scope, inm, pin_count(),
NetLogic::BUF);
break;
case BUFIF0:
cur[idx] = new NetLogic(scope, inm, pin_count(),
NetLogic::BUFIF0);
break;
case BUFIF1:
cur[idx] = new NetLogic(scope, inm, pin_count(),
NetLogic::BUFIF1);
break;
case NAND:
cur[idx] = new NetLogic(scope, inm, pin_count(),
NetLogic::NAND);
break;
case NMOS:
cur[idx] = new NetLogic(scope, inm, pin_count(),
NetLogic::NMOS);
break;
case NOR:
cur[idx] = new NetLogic(scope, inm, pin_count(),
NetLogic::NOR);
break;
case NOT:
cur[idx] = new NetLogic(scope, inm, pin_count(),
NetLogic::NOT);
break;
case NOTIF0:
cur[idx] = new NetLogic(scope, inm, pin_count(),
NetLogic::NOTIF0);
break;
case NOTIF1:
cur[idx] = new NetLogic(scope, inm, pin_count(),
NetLogic::NOTIF1);
break;
case OR:
cur[idx] = new NetLogic(scope, inm, pin_count(),
NetLogic::OR);
break;
case RNMOS:
cur[idx] = new NetLogic(scope, inm, pin_count(),
NetLogic::RNMOS);
break;
case RPMOS:
cur[idx] = new NetLogic(scope, inm, pin_count(),
NetLogic::RPMOS);
break;
case PMOS:
cur[idx] = new NetLogic(scope, inm, pin_count(),
NetLogic::PMOS);
break;
case PULLDOWN:
cur[idx] = new NetLogic(scope, inm, pin_count(),
NetLogic::PULLDOWN);
break;
case PULLUP:
cur[idx] = new NetLogic(scope, inm, pin_count(),
NetLogic::PULLUP);
break;
case XNOR:
cur[idx] = new NetLogic(scope, inm, pin_count(),
NetLogic::XNOR);
break;
case XOR:
cur[idx] = new NetLogic(scope, inm, pin_count(),
NetLogic::XOR);
break;
default:
cerr << get_line() << ": internal error: unhandled "
"gate type." << endl;
des->errors += 1;
return;
}
for (unsigned adx = 0 ; adx < attrib_list_n ; adx += 1)
cur[idx]->attribute(attrib_list[adx].key,
attrib_list[adx].val);
cur[idx]->rise_time(rise_time);
cur[idx]->fall_time(fall_time);
cur[idx]->decay_time(decay_time);
cur[idx]->pin(0).drive0(drive_type(strength0()));
cur[idx]->pin(0).drive1(drive_type(strength1()));
des->add_node(cur[idx]);
}
delete[]attrib_list;
/* The gates have all been allocated, this loop runs through
the parameters and attaches the ports of the objects. */
for (unsigned idx = 0 ; idx < pin_count() ; idx += 1) {
const PExpr*ex = pin(idx);
NetNet*sig = ex->elaborate_net(des, scope, 0, 0, 0, 0);
if (sig == 0)
continue;
assert(sig);
if (sig->pin_count() == 1)
for (unsigned gdx = 0 ; gdx < count ; gdx += 1)
connect(cur[gdx]->pin(idx), sig->pin(0));
else if (sig->pin_count() == count)
for (unsigned gdx = 0 ; gdx < count ; gdx += 1)
connect(cur[gdx]->pin(idx), sig->pin(gdx));
else {
cerr << get_line() << ": error: Gate count of " <<
count << " does not match net width of " <<
sig->pin_count() << " at pin " << idx << "."
<< endl;
des->errors += 1;
}
if (NetSubnet*tmp = dynamic_cast<NetSubnet*>(sig))
delete tmp;
}
}
/*
* Instantiate a module by recursively elaborating it. Set the path of
* the recursive elaboration so that signal names get properly
* set. Connect the ports of the instantiated module to the signals of
* the parameters. This is done with BUFZ gates so that they look just
* like continuous assignment connections.
*/
void PGModule::elaborate_mod_(Design*des, Module*rmod, NetScope*scope) const
{
// Missing module instance names have already been rejected.
assert(get_name() != "");
if (msb_) {
cerr << get_line() << ": sorry: Module instantiation arrays "
"are not yet supported." << endl;
des->errors += 1;
return;
}
assert(scope);
// I know a priori that the elaborate_scope created the scope
// already, so just look it up as a child of the current scope.
NetScope*my_scope = scope->child(get_name());
assert(my_scope);
const svector<PExpr*>*pins;
// Detect binding by name. If I am binding by name, then make
// up a pins array that reflects the positions of the named
// ports. If this is simply positional binding in the first
// place, then get the binding from the base class.
if (pins_) {
unsigned nexp = rmod->port_count();
svector<PExpr*>*exp = new svector<PExpr*>(nexp);
// Scan the bindings, matching them with port names.
for (unsigned idx = 0 ; idx < npins_ ; idx += 1) {
// Given a binding, look at the module port names
// for the position that matches the binding name.
unsigned pidx = rmod->find_port(pins_[idx].name);
// If the port name doesn't exist, the find_port
// method will return the port count. Detect that
// as an error.
if (pidx == nexp) {
cerr << get_line() << ": error: port ``" <<
pins_[idx].name << "'' is not a port of "
<< get_name() << "." << endl;
des->errors += 1;
continue;
}
// If I already bound something to this port, then
// the (*exp) array will already have a pointer
// value where I want to place this expression.
if ((*exp)[pidx]) {
cerr << get_line() << ": error: port ``" <<
pins_[idx].name << "'' already bound." <<
endl;
des->errors += 1;
continue;
}
// OK, do the binding by placing the expression in
// the right place.
(*exp)[pidx] = pins_[idx].parm;
}
pins = exp;
} else if (pin_count() == 0) {
/* Handle the special case that no ports are
connected. It is possible that this is an empty
connect-by-name list, su we'll allow it and assume
that is the case. */
svector<PExpr*>*tmp = new svector<PExpr*>(rmod->port_count());
for (unsigned idx = 0 ; idx < rmod->port_count() ; idx += 1)
(*tmp)[idx] = 0;
pins = tmp;
} else {
/* Otherwise, this is a positional list of fort
connections. In this case, the port count must be
right. Check that is is, the get the pin list. */
if (pin_count() != rmod->port_count()) {
cerr << get_line() << ": error: Wrong number "
"of ports. Expecting " << rmod->port_count() <<
", got " << pin_count() << "."
<< endl;
des->errors += 1;
return;
}
// No named bindings, just use the positional list I
// already have.
assert(pin_count() == rmod->port_count());
pins = get_pins();
}
// Elaborate this instance of the module. The recursive
// elaboration causes the module to generate a netlist with
// the ports represented by NetNet objects. I will find them
// later.
rmod->elaborate(des, my_scope);
// Now connect the ports of the newly elaborated designs to
// the expressions that are the instantiation parameters. Scan
// the pins, elaborate the expressions attached to them, and
// bind them to the port of the elaborated module.
// This can get rather complicated because the port can be
// unconnected (meaning an empty paramter is passed) connected
// to a concatenation, or connected to an internally
// unconnected port.
for (unsigned idx = 0 ; idx < pins->count() ; idx += 1) {
// Skip unconnected module ports. This happens when a
// null parameter is passed in.
if ((*pins)[idx] == 0)
continue;
// Inside the module, the port is zero or more signals
// that were already elaborated. List all those signals
// and the NetNet equivilents.
svector<PEIdent*> mport = rmod->get_port(idx);
svector<NetNet*>prts (mport.count());
// Count the internal pins of the port.
unsigned prts_pin_count = 0;
for (unsigned ldx = 0 ; ldx < mport.count() ; ldx += 1) {
PEIdent*pport = mport[ldx];
assert(pport);
prts[ldx] = pport->elaborate_port(des, my_scope);
if (prts[ldx] == 0)
continue;
assert(prts[ldx]);
prts_pin_count += prts[ldx]->pin_count();
}
// If I find that the port in unconnected inside the
// module, then there is nothing to connect. Skip the
// paramter.
if (prts_pin_count == 0) {
continue;
}
// Elaborate the expression that connects to the module
// port. sig is the thing outside the module that
// connects to the port.
NetNet*sig;
if ((prts.count() >= 1)
&& (prts[0]->port_type() != NetNet::PINPUT)) {
sig = (*pins)[idx]->elaborate_lnet(des, scope, true);
if (sig == 0) {
cerr << (*pins)[idx]->get_line() << ": error: "
<< "Output port expression must support "
<< "continuous assignment." << endl;
des->errors += 1;
continue;
}
} else {
sig = (*pins)[idx]->elaborate_net(des, scope,
prts_pin_count,
0, 0, 0);
if (sig == 0) {
cerr << "internal error: Expression too complicated "
"for elaboration." << endl;
continue;
}
}
assert(sig);
#ifndef NDEBUG
if ((prts.count() >= 1)
&& (prts[0]->port_type() != NetNet::PINPUT)) {
assert(sig->type() != NetNet::REG);
}
#endif
// Check that the parts have matching pin counts. If
// not, they are different widths. Note that idx is 0
// based, but users count parameter positions from 1.
if (prts_pin_count != sig->pin_count()) {
cerr << get_line() << ": warning: Port " << (idx+1)
<< " (" << rmod->ports[idx]->name << ") of "
<< type_ << " expects " << prts_pin_count <<
" bits, got " << sig->pin_count() << "." << endl;
if (prts_pin_count > sig->pin_count()) {
cerr << get_line() << ": : Leaving "
<< (prts_pin_count-sig->pin_count())
<< " high bits of the port unconnected."
<< endl;
} else {
cerr << get_line() << ": : Leaving "
<< (sig->pin_count()-prts_pin_count)
<< " high bits of the expression dangling."
<< endl;
}
}
// Connect the sig expression that is the context of the
// module instance to the ports of the elaborated module.
// The prts_pin_count variable is the total width of the
// port and is the maximum number of connections to
// make. sig is the elaborated expression that connects
// to that port. If sig has too few pins, then reduce
// the number of connections to make.
// Connect this many of the port pins. If the expression
// is too small, the reduce the number of connects.
unsigned ccount = prts_pin_count;
if (sig->pin_count() < ccount)
ccount = sig->pin_count();
// Now scan the concatenation that makes up the port,
// connecting pins until we run out of port pins or sig
// pins.
unsigned spin = 0;
for (unsigned ldx = prts.count() ; ldx > 0 ; ldx -= 1) {
unsigned cnt = prts[ldx-1]->pin_count();
if (cnt > ccount)
cnt = ccount;
for (unsigned p = 0 ; p < cnt ; p += 1) {
connect(sig->pin(spin), prts[ldx-1]->pin(p));
ccount -= 1;
spin += 1;
}
if (ccount == 0)
break;
}
if (NetSubnet*tmp = dynamic_cast<NetSubnet*>(sig))
delete tmp;
}
}
/*
* From a UDP definition in the source, make a NetUDP
* object. Elaborate the pin expressions as netlists, then connect
* those networks to the pins.
*/
void PGModule::elaborate_udp_(Design*des, PUdp*udp, NetScope*scope) const
{
string my_name = get_name();
if (my_name == "")
my_name = scope->local_hsymbol();
else
my_name = scope->name()+"."+my_name;
/* When the parser notices delay expressions in front of a
module or primitive, it interprets them as parameter
overrides. Correct that misconception here. */
unsigned long rise_time = 0, fall_time = 0, decay_time = 0;
if (overrides_) {
PDelays tmp_del;
tmp_del.set_delays(overrides_, false);
tmp_del.eval_delays(des, scope, rise_time, fall_time, decay_time);
}
NetUDP*net = new NetUDP(scope, my_name, udp->ports.count(), udp);
net->rise_time(rise_time);
net->fall_time(fall_time);
net->decay_time(decay_time);
struct attrib_list_t*attrib_list = 0;
unsigned attrib_list_n = 0;
attrib_list = evaluate_attributes(attributes, attrib_list_n,
des, scope);
for (unsigned adx = 0 ; adx < attrib_list_n ; adx += 1)
net->attribute(attrib_list[adx].key, attrib_list[adx].val);
delete[]attrib_list;
/* Run through the pins, making netlists for the pin
expressions and connecting them to the pin in question. All
of this is independent of the nature of the UDP. */
for (unsigned idx = 0 ; idx < net->pin_count() ; idx += 1) {
if (pin(idx) == 0)
continue;
NetNet*sig = pin(idx)->elaborate_net(des, scope, 1, 0, 0, 0);
if (sig == 0) {
cerr << "internal error: Expression too complicated "
"for elaboration:" << *pin(idx) << endl;
continue;
}
connect(sig->pin(0), net->pin(idx));
// Delete excess holding signal.
if (NetSubnet*tmp = dynamic_cast<NetSubnet*>(sig))
delete tmp;
}
// All done. Add the object to the design.
des->add_node(net);
}
bool PGModule::elaborate_sig(Design*des, NetScope*scope) const
{
// Look for the module type
map<string,Module*>::const_iterator mod = pform_modules.find(type_);
if (mod != pform_modules.end())
return elaborate_sig_mod_(des, scope, (*mod).second);
return true;
}
void PGModule::elaborate(Design*des, NetScope*scope) const
{
// Look for the module type
map<string,Module*>::const_iterator mod = pform_modules.find(type_);
if (mod != pform_modules.end()) {
elaborate_mod_(des, (*mod).second, scope);
return;
}
// Try a primitive type
map<string,PUdp*>::const_iterator udp = pform_primitives.find(type_);
if (udp != pform_primitives.end()) {
elaborate_udp_(des, (*udp).second, scope);
return;
}
cerr << get_line() << ": internal error: Unknown module type: " <<
type_ << endl;
}
void PGModule::elaborate_scope(Design*des, NetScope*sc) const
{
// Look for the module type
map<string,Module*>::const_iterator mod = pform_modules.find(type_);
if (mod != pform_modules.end()) {
elaborate_scope_mod_(des, (*mod).second, sc);
return;
}
// Try a primitive type
map<string,PUdp*>::const_iterator udp = pform_primitives.find(type_);
if (udp != pform_primitives.end())
return;
// Not a module or primitive that I know about yet, so try to
// load a library module file (which parses some new Verilog
// code) and try again.
if (load_module(type_)) {
// Try again to find the module type
mod = pform_modules.find(type_);
if (mod != pform_modules.end()) {
elaborate_scope_mod_(des, (*mod).second, sc);
return;
}
// Try again to find a primitive type
udp = pform_primitives.find(type_);
if (udp != pform_primitives.end())
return;
}
// Not a module or primitive that I know about or can find by
// any means, so give up.
cerr << get_line() << ": error: Unknown module type: " << type_ << endl;
des->errors += 1;
}
NetProc* Statement::elaborate(Design*des, NetScope*) const
{
cerr << get_line() << ": internal error: elaborate: "
"What kind of statement? " << typeid(*this).name() << endl;
NetProc*cur = new NetProc;
des->errors += 1;
return cur;
}
NetAssign_* PAssign_::elaborate_lval(Design*des, NetScope*scope) const
{
assert(lval_);
return lval_->elaborate_lval(des, scope);
}
/*
* This function elaborates delay expressions. This is a little
* different from normal elaboration because the result may need to be
* scaled.
*/
static NetExpr*elaborate_delay_expr(PExpr*expr, Design*des, NetScope*scope)
{
if (verireal*dr = expr->eval_rconst(des, scope)) {
int shift = scope->time_unit() - des->get_precision();
long val = dr->as_long(shift);
delete dr;
return new NetEConst(verinum(val));
}
if (verinum*dv = expr->eval_const(des, scope)) {
unsigned long val = dv->as_ulong();
val = des->scale_to_precision(val, scope);
return new NetEConst(verinum(val));
}
NetExpr*delay = expr->elaborate_expr(des, scope);
int shift = scope->time_unit() - des->get_precision();
if (shift > 0) {
unsigned long scale = 1;
while (shift > 0) {
scale *= 10;
shift -= 1;
}
NetExpr*scal_val = new NetEConst(verinum(scale));
delay = new NetEBMult('*', delay, scal_val);
}
if (shift < 0) {
unsigned long scale = 1;
while (shift < 0) {
scale *= 10;
shift += 1;
}
NetExpr*scal_val = new NetEConst(verinum(scale));
delay = new NetEBDiv('/', delay, scal_val);
}
return delay;
}
NetProc* PAssign::elaborate(Design*des, NetScope*scope) const
{
assert(scope);
/* elaborate the lval. This detects any part selects and mux
expressions that might exist. */
NetAssign_*lv = elaborate_lval(des, scope);
if (lv == 0) return 0;
/* If there is an internal delay expression, elaborate it. */
NetExpr*delay = 0;
if (delay_ != 0)
delay = elaborate_delay_expr(delay_, des, scope);
/* Elaborate the r-value expression. */
assert(rval());
NetExpr*rv;
if (verinum*val = rval()->eval_const(des, scope)) {
rv = new NetEConst(*val);
delete val;
} else if (rv = rval()->elaborate_expr(des, scope)) {
/* OK, go on. */
} else {
/* Unable to elaborate expression. Retreat. */
return 0;
}
assert(rv);
/* Try to evaluate the expression, at least as far as possible. */
if (NetExpr*tmp = rv->eval_tree()) {
delete rv;
rv = tmp;
}
/* Rewrite delayed assignments as assignments that are
delayed. For example, a = #<d> b; becomes:
begin
tmp = b;
#<d> a = tmp;
end
If the delay is an event delay, then the transform is
similar, with the event delay replacing the time delay. It
is an event delay if the event_ member has a value.
This rewriting of the expression allows me to not bother to
actually and literally represent the delayed assign in the
netlist. The compound statement is exactly equivalent. */
if (delay || event_) {
string n = scope->local_hsymbol();
unsigned wid = lv->lwidth();
rv->set_width(wid);
rv = pad_to_width(rv, wid);
if (wid != rv->expr_width()) {
cerr << get_line() << ": error: Unable to match "
"expression width of " << rv->expr_width() <<
" to l-value width of " << wid << "." << endl;
//XXXX delete rv;
return 0;
}
NetNet*tmp = new NetNet(scope, n, NetNet::REG, wid);
tmp->set_line(*this);
NetESignal*sig = new NetESignal(tmp);
/* Generate an assignment of the l-value to the temporary... */
n = scope->local_hsymbol();
NetAssign_*lvt = new NetAssign_(tmp);
NetAssign*a1 = new NetAssign(lvt, rv);
a1->set_line(*this);
/* Generate an assignment of the temporary to the r-value... */
NetAssign*a2 = new NetAssign(lv, sig);
a2->set_line(*this);