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Allow variables to implicitly convert to unresolved nets.
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SystemVerilog allows variables to be either variables or unresolved
nets, depending on how they are used. If they are assigned by
procedural code, then they are variables. If they are assigned
by a continuous assignment, they are unresolved nets. Note that
they cannot be both, and when they are unresolved nets they can
only be assigned once.
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steveicarus committed Oct 10, 2010
1 parent 6a0cbc5 commit 568ee44
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Showing 6 changed files with 31 additions and 5 deletions.
10 changes: 10 additions & 0 deletions compiler.h
Expand Up @@ -151,6 +151,16 @@ extern bool gn_io_range_error_flag;
re-evaluated. */
extern bool gn_strict_ca_eval_flag;

/* If variables can be converted to uwires by a continuous assignment
(assuming no procedural assign, then return true. This will be true
for SystemVerilog */
static inline bool gn_var_can_be_uwire(void)
{
if (generation_flag == GN_VER2009)
return true;
return false;
}

/* The bits of these GN_KEYWORDS_* constants define non-intersecting
sets of keywords. The compiler enables groups of keywords by setting
lexor_keyword_mask with the OR of the bits for the keywords to be
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16 changes: 16 additions & 0 deletions elab_net.cc
Expand Up @@ -414,6 +414,22 @@ NetNet* PEIdent::elaborate_lnet_common_(Design*des, NetScope*scope,

assert(sig);

/* If this is SystemVerilog and the variable is not yet
assigned by anything, then convert it to an unresolved
wire. */
if (gn_var_can_be_uwire()
&& (sig->type() == NetNet::REG)
&& (sig->peek_eref() == 0) ) {
sig->type(NetNet::UNRESOLVED_WIRE);
}

if (sig->type() == NetNet::UNRESOLVED_WIRE && sig->pin(0).is_linked()) {
cerr << get_fileline() << ": error: Unresolved net " << sig->name()
<< " cannot have multiple drivers." << endl;
des->errors += 1;
return 0;
}

/* Don't allow registers as assign l-values. */
if (sig->type() == NetNet::REG) {
cerr << get_fileline() << ": error: reg " << sig->name()
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2 changes: 1 addition & 1 deletion netlist.cc
Expand Up @@ -78,7 +78,7 @@ ostream& operator<< (ostream&o, NetNet::Type t)
case NetNet::WIRE:
o << "wire";
break;
case NetNet::UWIRE:
case NetNet::UNRESOLVED_WIRE:
o << "uwire";
}
return o;
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2 changes: 1 addition & 1 deletion netlist.h
Expand Up @@ -553,7 +553,7 @@ class NetNet : public NetObj {
public:
enum Type { NONE, IMPLICIT, IMPLICIT_REG, INTEGER, WIRE, TRI, TRI1,
SUPPLY0, SUPPLY1, WAND, TRIAND, TRI0, WOR, TRIOR, REG,
UWIRE };
UNRESOLVED_WIRE };

enum PortType { NOT_A_PORT, PIMPLICIT, PINPUT, POUTPUT, PINOUT };

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4 changes: 2 additions & 2 deletions parse.y
Expand Up @@ -2708,12 +2708,12 @@ net_type
| K_supply1 { $$ = NetNet::SUPPLY1; }
| K_wor { $$ = NetNet::WOR; }
| K_trior { $$ = NetNet::TRIOR; }
| K_wone { $$ = NetNet::UWIRE;
| K_wone { $$ = NetNet::UNRESOLVED_WIRE;
cerr << @1.text << ":" << @1.first_line << ": warning: "
"'wone' is deprecated, please use 'uwire' "
"instead." << endl;
}
| K_uwire { $$ = NetNet::UWIRE; }
| K_uwire { $$ = NetNet::UNRESOLVED_WIRE; }
;

var_type
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2 changes: 1 addition & 1 deletion t-dll.cc
Expand Up @@ -2386,7 +2386,7 @@ void dll_target::signal(const NetNet*net)

/* We will convert this to a TRI after we check that there
is only one driver. */
case NetNet::UWIRE:
case NetNet::UNRESOLVED_WIRE:
obj->type_ = IVL_SIT_UWIRE;
break;

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