Merge branch 'master' into elaborate-net-rework

steveicarus · Sep 7, 2008 · dd47599 · dd47599
2 parents 5f0b723 + 8717a85
commit dd47599
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Showing 48 changed files with 237 additions and 194 deletions.
diff --git a/Statement.h b/Statement.h
@@ -82,6 +82,8 @@ class Statement : public LineInfo {
       virtual NetProc* elaborate(Design*des, NetScope*scope) const;
       virtual void elaborate_scope(Design*des, NetScope*scope) const;
       virtual void elaborate_sig(Design*des, NetScope*scope) const;
+
+      map<perm_string,PExpr*> attributes;
 };
 
 /*

diff --git a/constants.vams b/constants.vams
@@ -3,7 +3,7 @@
 `ifdef CONSTANTS_VAMS
 `else
 `define CONSTANTS_VAMS 1
- 
+
 // M_ is a mathematical constant
 `define M_E        2.7182818284590452354
 `define M_LOG2E    1.4426950408889634074

diff --git a/driver/cflexor.lex b/driver/cflexor.lex
@@ -149,7 +149,7 @@ int cmdfile_stack_ptr = 0;
       cflval.text = trim_trailing_white(yytext, 0);
       BEGIN(0);
       return TOK_STRING; }
-       
+
   /* Fallback match. */
 . { return yytext[0]; }
 

diff --git a/driver/iverilog.man b/driver/iverilog.man
@@ -221,7 +221,7 @@ implies the synthesis \fB-S\fP flag.
 .TP 8
 .B vhdl
 This target produces a VHDL translation of the Verilog netlist. The
-output is a single file containing VHDL entities corresponding to 
+output is a single file containing VHDL entities corresponding to
 the modules in the Verilog source code. Note that only a subset of
 the Verilog language is supported.  See the wiki for more information.
 

diff --git a/driver/main.c b/driver/main.c
@@ -341,7 +341,7 @@ static int t_default(char*cmd, unsigned ncmd)
 	    } else {
 		  fprintf(stderr, "Command signaled: %s\n", cmd);
 		  rtn = -1;
-	    } 
+	    }
       }
 
       free(cmd);
@@ -523,7 +523,7 @@ int process_generation(const char*name)
 void add_sft_file(const char *module)
 {
       char *file;
-   
+
       file = (char *) malloc(strlen(base)+1+strlen(module)+4+1);
       sprintf(file, "%s%c%s.sft", base, sep, module);
       if (access(file, R_OK) == 0)
@@ -654,7 +654,7 @@ int main(int argc, char **argv)
 		case 'c':
 		case 'f':
 		  add_cmd_file(optarg);
- 		  break;
+		  break;
 		case 'D':
 		  process_define(optarg);
 		  break;
@@ -673,9 +673,9 @@ int main(int argc, char **argv)
 		  if (rc != 0)
 			return -1;
 		  break;
- 		case 'h':
- 		  fprintf(stderr, "%s\n", HELP);
- 		  return 1;
+		case 'h':
+		  fprintf(stderr, "%s\n", HELP);
+		  return 1;
 
 		case 'I':
 		  process_include_dir(optarg);

diff --git a/elab_expr.cc b/elab_expr.cc
@@ -682,7 +682,7 @@ NetExpr* PECallFunction::elaborate_sfunc_(Design*des, NetScope*scope, int expr_w
 	      /* Elaborate the sub-expression to get its
 		 self-determined width, and save that width. Then
 		 delete the expression because we don't really want
-		 the expression itself. */ 
+		 the expression itself. */
 	    long sub_expr_width = 0;
 	    if (NetExpr*tmp = expr->elaborate_expr(des, scope, -1, true)) {
 		  sub_expr_width = tmp->expr_width();

diff --git a/elab_net.cc b/elab_net.cc
@@ -394,15 +394,15 @@ static NetNet* compare_eq_constant(Design*des, NetScope*scope,
 	    if (zeros > 0) {
 		  type = op_code == 'e'? NetUReduce::NOR : NetUReduce::OR;
 
-		  if (debug_elaborate) 
+		  if (debug_elaborate)
 			cerr << lsig->get_fileline() << ": debug: "
 			     << "Replace net==" << val << " equality with "
 			     << zeros << "-input reduction [N]OR gate." << endl;
 
 	    } else {
 		  type = op_code == 'e'? NetUReduce::AND : NetUReduce::NAND;
 
-		  if (debug_elaborate) 
+		  if (debug_elaborate)
 			cerr << lsig->get_fileline() << ": debug: "
 			     << "Replace net==" << val << " equality with "
 			     << ones << "-input reduction AND gate." << endl;
@@ -1227,8 +1227,8 @@ NetNet* PEBinary::elaborate_net_shift_(Design*des, NetScope*scope,
 	    }
 
 	    /* If all data bits get shifted away, connect the zero or
- 	     * padding bits directly to output, and stop before building the
- 	     * concatenation. */
+	     * padding bits directly to output, and stop before building the
+	     * concatenation. */
 	    if (dist >= lwidth) {
 		  connect(osig->pin(0), zero->pin(0));
 		  return osig;
@@ -1829,7 +1829,7 @@ NetNet* PEIdent::elaborate_net(Design*des, NetScope*scope,
 	    if (id_msb || id_lsb) {
 		  assert(id_msb && id_lsb);
 		  const NetEConst*tmp = dynamic_cast<const NetEConst*>(id_msb);
-		  ivl_assert(*this, tmp);		  
+		  ivl_assert(*this, tmp);
 		  msb = tmp->value().as_long();
 
 		  tmp = dynamic_cast<const NetEConst*>(id_lsb);
@@ -2997,7 +2997,7 @@ NetNet* PENumber::elaborate_net(Design*des, NetScope*scope,
 			if (value_->get(width-1) != verinum::V0)
 			      break;
 			width -= 1;
-		  
+
 	    }
 
 	    } else if (value_->has_sign() == false) {
@@ -3406,7 +3406,7 @@ NetNet* PEUnary::elaborate_net(Design*des, NetScope*scope,
 	      tmp->decay_time(decay);
 
 	      connect(tmp->pin(1), sub_sig->pin(0));
-	      connect(tmp->pin(0), sig->pin(0));	    
+	      connect(tmp->pin(0), sig->pin(0));
 	    }
 	    break;
 
@@ -3662,7 +3662,7 @@ NetNet* PEUnary::elab_net_unary_real_(Design*des, NetScope*scope,
 		    " for real values." << endl;
 	    des->errors += 1;
 	    break;
- 
+
 	  case 'm': { // abs()
 		NetAbs*tmp = new NetAbs(scope, scope->local_symbol(), 1);
 		tmp->set_line(*this);

diff --git a/elab_scope.cc b/elab_scope.cc
@@ -670,7 +670,7 @@ bool PGenerate::generate_scope_case_(Design*des, NetScope*container)
 		 << "Generate case matches item at "
 		 << item->get_fileline() << endl;
 
- 	// The name of the scope to generate, whatever that item is.
+	// The name of the scope to generate, whatever that item is.
       hname_t use_name (item->scope_name);
 
       NetScope*scope = new NetScope(container, use_name,

diff --git a/elab_sig.cc b/elab_sig.cc
@@ -143,7 +143,7 @@ static void elaborate_sig_tasks(Design*des, NetScope*scope,
       }
 }
 
-				
+
 bool Module::elaborate_sig(Design*des, NetScope*scope) const
 {
       bool flag = true;
@@ -361,7 +361,7 @@ bool PGModule::elaborate_sig_mod_(Design*des, NetScope*scope,
 			continue;
 		  flag = tmp->elaborate_sig(des, scope) && flag;
 	    }
-	    
+
 
       NetScope::scope_vec_t instance = scope->instance_arrays[get_name()];
 

diff --git a/eval_tree.cc b/eval_tree.cc
@@ -1377,7 +1377,7 @@ NetExpr* NetETernary::eval_tree(int prune_to_width)
 	  case C_0:
 	    eval_expr(false_val_);
 	    if (debug_eval_tree) {
-		  
+
 		  cerr << get_fileline() << ": debug: Evaluate ternary with "
 		       << "constant condition value: ";
 		  print_ternary_cond(cond_);

diff --git a/expr_synth.cc b/expr_synth.cc
@@ -1269,7 +1269,7 @@ NetNet* NetEUFunc::synthesize(Design*des, NetScope*scope)
         /* Connect the pins to the arguments. */
       NetFuncDef*def = func_->func_def();
       for (unsigned idx = 0; idx < eparms.count(); idx += 1) {
-	    NetNet*tmp = pad_to_width(des, eparms[idx], 
+	    NetNet*tmp = pad_to_width(des, eparms[idx],
 	                              def->port(idx)->vector_width());
 	    connect(net->pin(idx+1), tmp->pin(0));
       }

diff --git a/ivlpp/main.c b/ivlpp/main.c
@@ -282,7 +282,7 @@ int main(int argc, char*argv[])
 		fclose(src);
 		break;
 	  }
-		
+
 	  case 'v':
 	    fprintf(stderr, "Icarus Verilog Preprocessor version %s\n",
 		    VERSION);

diff --git a/libveriuser/a_object_of_type.c b/libveriuser/a_object_of_type.c
@@ -35,7 +35,7 @@ int acc_object_of_type(handle object, PLI_INT32 type)
 
       if (pli_trace) {
 	    fprintf(pli_trace, "acc_object_of_type(%p \"%s\", %d)",
-	    	object, vpi_get_str(vpiName, object), type);
+		object, vpi_get_str(vpiName, object), type);
 	    fflush(pli_trace);
       }
 

diff --git a/main.cc b/main.cc
@@ -230,16 +230,16 @@ static void process_generation_flag(const char*gen)
 
       } else if (strcmp(gen,"specify") == 0) {
 	    gn_specify_blocks_flag = true;
- 
+
       } else if (strcmp(gen,"no-specify") == 0) {
 	    gn_specify_blocks_flag = false;
- 
+
       } else if (strcmp(gen,"verilog-ams") == 0) {
 	    gn_verilog_ams_flag = true;
- 
+
       } else if (strcmp(gen,"no-verilog-ams") == 0) {
 	    gn_verilog_ams_flag = false;
- 
+
       } else if (strcmp(gen,"io-range-error") == 0) {
 	    gn_io_range_error_flag = true;
 

diff --git a/netlist.h b/netlist.h
@@ -736,7 +736,7 @@ class NetScope : public Attrib {
       bool in_func();
 	/* Is the task or function automatic. */
       void is_auto(bool is_auto) { is_auto_ = is_auto; };
-      bool is_auto() const { return is_auto_; }; 
+      bool is_auto() const { return is_auto_; };
 
       const NetTaskDef* task_def() const;
       const NetFuncDef* func_def() const;
@@ -773,7 +773,7 @@ class NetScope : public Attrib {
 
       void evaluate_parameters(class Design*);
 
-      	// Look for defparams that never matched, and print warnings.
+	// Look for defparams that never matched, and print warnings.
       void residual_defparams(class Design*);
 
 	/* This method generates a non-hierarchical name that is

diff --git a/parse.y b/parse.y
@@ -355,7 +355,7 @@ number  : BASED_NUMBER
 	       based_size = 0; }
 	;
 
-  /* real and realtime are exactly the same so save some code 
+  /* real and realtime are exactly the same so save some code
    * with a common matching rule. */
 real_or_realtime
 	: K_real
@@ -3591,28 +3591,31 @@ statement
 		  FILE_NAME(tmp, @1);
 		  $$ = tmp;
 		}
-	| event_control statement_or_null
-		{ PEventStatement*tmp = $1;
-		  if (tmp == 0) {
-			yyerror(@1, "error: Invalid event control.");
-			$$ = 0;
-		  } else {
-			tmp->set_statement($2);
-			$$ = tmp;
-		  }
-		}
-	| '@' '*' statement_or_null
-		{ PEventStatement*tmp = new PEventStatement;
-		  FILE_NAME(tmp, @1);
-		  tmp->set_statement($3);
-		  $$ = tmp;
-		}
-	| '@' '(' '*' ')' statement_or_null
-		{ PEventStatement*tmp = new PEventStatement;
-		  FILE_NAME(tmp, @1);
-		  tmp->set_statement($5);
-		  $$ = tmp;
-		}
+  | event_control attribute_list_opt statement_or_null
+      { PEventStatement*tmp = $1;
+	if (tmp == 0) {
+	      yyerror(@1, "error: Invalid event control.");
+	      $$ = 0;
+	} else {
+	      if ($3) pform_bind_attributes($3->attributes,$2);
+	      tmp->set_statement($3);
+	      $$ = tmp;
+	}
+      }
+  | '@' '*' attribute_list_opt statement_or_null
+      { PEventStatement*tmp = new PEventStatement;
+	FILE_NAME(tmp, @1);
+	if ($4) pform_bind_attributes($4->attributes,$3);
+	tmp->set_statement($4);
+	$$ = tmp;
+      }
+  | '@' '(' '*' ')' attribute_list_opt statement_or_null
+      { PEventStatement*tmp = new PEventStatement;
+	FILE_NAME(tmp, @1);
+	if ($6) pform_bind_attributes($6->attributes,$5);
+	tmp->set_statement($6);
+	$$ = tmp;
+      }
 	| lpvalue '=' expression ';'
 		{ PAssign*tmp = new PAssign($1,$3);
 		  FILE_NAME(tmp, @1);
@@ -3737,14 +3740,15 @@ statement_list
 	;
 
 statement_or_null
-	: statement
-	| ';' { $$ = 0; }
-	;
-
+  : statement
+      { $$ = $1; }
+  | ';'
+      { $$ = 0; }
+  ;
 
 analog_statement
   : branch_probe_expression K_CONTRIBUTE expression ';'
-  { $$ = pform_contribution_statement(@2, $1, $3); }
+      { $$ = pform_contribution_statement(@2, $1, $3); }
   ;
 
   /* Task items are, other than the statement, task port items and
@@ -3970,7 +3974,7 @@ task_port_decl
 		}
 
   /* Ports can be integer with a width of [31:0]. */
- 
+
 	| K_input K_integer IDENTIFIER
                 { svector<PExpr*>*range_stub = new svector<PExpr*>(2);
 		  PExpr*re;
@@ -4036,7 +4040,7 @@ task_port_decl
 		}
 
   /* Ports can be time with a width of [63:0] (unsigned). */
- 
+
 	| K_input K_time IDENTIFIER
                 { svector<PExpr*>*range_stub = new svector<PExpr*>(2);
 		  PExpr*re;

diff --git a/pform.cc b/pform.cc
@@ -157,6 +157,19 @@ PBlock* pform_push_block_scope(char*name, PBlock::BL_TYPE bt)
       return block;
 }
 
+void pform_bind_attributes(map<perm_string,PExpr*>&attributes,
+			   svector<named_pexpr_t*>*attr)
+{
+      if (attr == 0)
+	    return;
+
+      for (unsigned idx = 0 ;  idx < attr->count() ;  idx += 1) {
+	    named_pexpr_t*tmp = (*attr)[idx];
+	    attributes[tmp->name] = tmp->parm;
+      }
+      delete attr;
+}
+
 PWire*pform_get_wire_in_scope(perm_string name)
 {
 	/* Note that if we are processing a generate, then the
@@ -1951,13 +1964,7 @@ PProcess* pform_make_behavior(PProcess::Type type, Statement*st,
 {
       PProcess*pp = new PProcess(type, st);
 
-      if (attr) {
-	    for (unsigned idx = 0 ;  idx < attr->count() ;  idx += 1) {
-		  named_pexpr_t*tmp = (*attr)[idx];
-		  pp->attributes[tmp->name] = tmp->parm;
-	    }
-	    delete attr;
-      }
+      pform_bind_attributes(pp->attributes, attr);
 
       pform_put_behavior_in_scope(pp);
       return pp;

diff --git a/pform.h b/pform.h
@@ -117,6 +117,10 @@ struct lgate {
       unsigned lineno;
 };
 
+  /* Use this function to transform the parted form of the attribute
+     list to the attribute map that is used later. */
+extern void pform_bind_attributes(map<perm_string,PExpr*>&attributes,
+				  svector<named_pexpr_t*>*attr);
 
   /* The lexor calls this function to change the default nettype. */
 extern void pform_set_default_nettype(NetNet::Type net,