ivl: logic_lpm.c:463: emit_nexus_port_signal: Assertion `! sig' failed.

[vicencb]

Hi,
this verilog code assigning the same wire to two different ports through two levels of hierarchy triggers an assertion failure.

module a ();
  wire aw;
  b b_inst ( .first(aw), .second(aw) );
endmodule

module b ( input wire first, input wire second );
  c c_inst ( .first(first), .second(second) );
endmodule

module c ( input wire first, input wire second );
endmodule

To reproduce execute this:
iverilog -tvlog95 test.v