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The following module should set the output to constant 0, because the 4'b0 makes the whole expression unsigned.
module issue_032(y);
wire signed [3:0] a = -5;
wire signed [3:0] b = 0;
output y;
assign y = (1 ? a : 4'b0) < (1 ? b : b);
initial #1 $display("%b", y);
endmodule
But Icarus Verilog (git 3e41a93) assigns 1 instead. Interestingly the bug goes away if the (1 ? b : b) is replaced by b.
The text was updated successfully, but these errors were encountered:
I've pushed a fix for this to the git master branch. The compiler was correctly determining that the expression was unsigned, but losing this information during optimisation of the ternary expressions.
The following module should set the output to constant 0, because the 4'b0 makes the whole expression unsigned.
But Icarus Verilog (git 3e41a93) assigns 1 instead. Interestingly the bug goes away if the (1 ? b : b) is replaced by b.
The text was updated successfully, but these errors were encountered: