Another assert for invalid input

[cliffordwolf]

Iverilog 6547fde triggers an assert on the following (invalid) code:

module tb;
  wire [3:0] a, y;
  test uut (.a(a), .y(y));
endmodule

module test(a, b, y);
  input [3:0] a;
  output [3:0] y;
  assign y = a;
endmodule

The output I get is:

test.v:6: error: Port b (2) of module test is not declared within module.
ivl: elaborate.cc:1310: void PGModule::elaborate_mod_(Design*, Module*, NetScope*) const: Assertion `tmp' failed.

[martinwhitaker]

I've pushed a fix for this to the master branch.