Merge branch 'master' of github.com:steveicarus/ivtest

steveicarus · Feb 17, 2017 · 07f562f · 07f562f
2 parents 8ef38ff + cd71f26
commit 07f562f
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Showing 6 changed files with 17 additions and 4 deletions.
diff --git a/ivltests/br_gh142.v b/ivltests/br_gh142.v
@@ -0,0 +1,8 @@
+module test();
+
+parameter y = 1;
+parameter a = 0;
+
+parameter x = y ? a : b;
+
+endmodule
diff --git a/regress-vlg.list b/regress-vlg.list
@@ -285,6 +285,7 @@ br_gh127c		normal			ivltests gold=br_gh127c.gold
 br_gh127d		normal			ivltests gold=br_gh127d.gold
 br_gh127e		normal			ivltests gold=br_gh127e.gold
 br_gh127f		normal			ivltests gold=br_gh127f.gold
+br_gh142		CE			ivltests
 br_ml_20150315		normal			ivltests gold=br_ml_20150315.gold
 br_ml_20150321		CE			ivltests
 br_ml_20150606		normal			ivltests

diff --git a/regression_report-devel.txt b/regression_report-devel.txt
@@ -376,6 +376,7 @@ Running compiler/VVP tests for Icarus Verilog version: 11.
                   br_gh127d: Passed.
                   br_gh127e: Passed.
                   br_gh127f: Passed.
+                   br_gh142: Passed - CE.
              br_ml_20150315: Passed.
              br_ml_20150321: Passed - CE.
              br_ml_20150606: Passed.
@@ -2279,4 +2280,4 @@ test_mos_strength_reduction: Passed.
                 ufuncsynth1: Passed.
 ============================================================================
 Test results:
-  Total=2277, Passed=2270, Failed=7, Not Implemented=0, Expected Fail=0
+  Total=2278, Passed=2271, Failed=7, Not Implemented=0, Expected Fail=0
diff --git a/regression_report-strict.txt b/regression_report-strict.txt
@@ -369,6 +369,7 @@ Running compiler/VVP tests for Icarus Verilog version: 11 (strict).
                   br_gh127d: Passed.
                   br_gh127e: Passed.
                   br_gh127f: Passed.
+                   br_gh142: Passed - CE.
              br_ml_20150315: Passed.
              br_ml_20150321: Passed - CE.
              br_ml_20150606: Passed.
@@ -2276,4 +2277,4 @@ test_mos_strength_reduction: Passed.
                 ufuncsynth1: Passed.
 ============================================================================
 Test results:
-  Total=2274, Passed=2267, Failed=7, Not Implemented=0, Expected Fail=0
+  Total=2275, Passed=2268, Failed=7, Not Implemented=0, Expected Fail=0
diff --git a/regression_report-v10.txt b/regression_report-v10.txt
@@ -434,6 +434,7 @@ Running compiler/VVP tests for Icarus Verilog version: 10.
                   br_gh127d: Passed.
                   br_gh127e: Passed.
                   br_gh127f: Passed.
+                   br_gh142: Passed - CE.
              br_ml_20150315: Passed.
              br_ml_20150321: Passed - CE.
              br_ml_20150606: Passed.
@@ -2279,4 +2280,4 @@ test_mos_strength_reduction: Passed.
                 ufuncsynth1: Passed.
 ============================================================================
 Test results:
-  Total=2277, Passed=2243, Failed=4, Not Implemented=30, Expected Fail=0
+  Total=2278, Passed=2244, Failed=4, Not Implemented=30, Expected Fail=0
diff --git a/regression_report-vlog95.txt b/regression_report-vlog95.txt
@@ -915,6 +915,7 @@ Running vlog95 compiler/VVP tests for Icarus Verilog version: 11.
                    br_gh103: Passed.
                   br_gh127a: Passed.
                   br_gh127d: Passed.
+                   br_gh142: Passed - CE.
              br_ml_20150315: Passed.
              br_ml_20150321: Passed - CE.
              br_ml_20150606: Passed.
@@ -2279,4 +2280,4 @@ test_mos_strength_reduction: Passed.
            synth_if_no_else: Passed.
 ============================================================================
 Test results:
-  Total=2277, Passed=2239, Failed=5, Not Implemented=3, Expected Fail=30
+  Total=2278, Passed=2240, Failed=5, Not Implemented=3, Expected Fail=30