F4: flash rework - remove compiler warnings

stevstrong · Jan 12, 2020 · 7c621b2 · 7c621b2
1 parent 2cbdbe0
commit 7c621b2
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Showing 3 changed files with 35 additions and 107 deletions.
diff --git a/STM32F4/cores/maple/libmaple/flash.c b/STM32F4/cores/maple/libmaple/flash.c
diff --git a/STM32F4/cores/maple/libmaple/flash.h b/STM32F4/cores/maple/libmaple/flash.h
@@ -52,7 +52,7 @@ typedef struct flash_reg_map {
 } flash_reg_map;
 
 /** Flash register map base pointer */
-#define FLASH_BASE                     ((struct flash_reg_map*)0x40023C00)
+#define FLASH                          ((struct flash_reg_map*)0x40023C00)
 
 // taken from CMSIS
 #define UID_BASE         0x1FFF7A10U // Unique device ID register base address
@@ -224,9 +224,35 @@ typedef struct flash_reg_map {
  * Setup routines
  */
 
-void flash_enable_ART(void);
-void flash_disable_ART(void);
-void flash_set_latency(uint32 wait_states);
+// Turn on the hardware 'ART accelerator' i.e. prefetch + data & instruction cache
+static inline void flash_init(uint32 acr_latency) {
+	FLASH->ACR = (FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN) | acr_latency;
+}
+
+// Enable prefetch buffer, instruction cache and data cache
+static inline void flash_enable_ART(void) {
+	FLASH->ACR |= FLASH_ACR_PRFTEN;
+}
+
+// Disable prefetch buffer, instruction cache and data cache
+static inline void flash_disable_ART(void) {
+	FLASH->ACR &= ~(FLASH_ACR_PRFTEN);
+}
+
+/**
+ * @brief Set flash wait states
+ *
+ * See ST PM0042, section 3.1 for restrictions on the acceptable value
+ * of wait_states for a given SYSCLK configuration.
+ *
+ * @param wait_states number of wait states (one of
+ *                    FLASH_ACR_LATENCY_0WS .. FLASH_ACR_LATENCY_7WS
+ */
+static inline void flash_set_latency(uint32 wait_states) {
+    uint32 val = FLASH->ACR & ~(FLASH_ACR_LATENCY_Msk);
+    FLASH->ACR = val | wait_states;
+}
+
 
 #ifdef __cplusplus
 }

diff --git a/STM32F4/cores/maple/libmaple/rccF4.c b/STM32F4/cores/maple/libmaple/rccF4.c
@@ -134,38 +134,6 @@ static const struct rcc_dev_info rcc_dev_table[] = {
  * @param pll_mul pll multiplier
  */
 
-/*******************  Bits definition for FLASH_ACR register  *****************/
-//#define FLASH_ACR_LATENCY                    ((uint32_t)0x00000007)
-#define FLASH_ACR_LATENCY_0WS                ((uint32)0x00000000)
-#define FLASH_ACR_LATENCY_1WS                ((uint32)0x00000001)
-#define FLASH_ACR_LATENCY_2WS                ((uint32)0x00000002)
-#define FLASH_ACR_LATENCY_3WS                ((uint32)0x00000003)
-#define FLASH_ACR_LATENCY_4WS                ((uint32)0x00000004)
-#define FLASH_ACR_LATENCY_5WS                ((uint32)0x00000005)
-#define FLASH_ACR_LATENCY_6WS                ((uint32)0x00000006)
-#define FLASH_ACR_LATENCY_7WS                ((uint32)0x00000007)
-
-#define FLASH_ACR_PRFTEN                     ((uint32)0x00000100)
-#define FLASH_ACR_ICEN                       ((uint32)0x00000200)
-#define FLASH_ACR_DCEN                       ((uint32)0x00000400)
-#define FLASH_ACR_ICRST                      ((uint32)0x00000800)
-#define FLASH_ACR_DCRST                      ((uint32)0x00001000)
-#define FLASH_ACR_BYTE0_ADDRESS              ((uint32)0x40023C00)
-#define FLASH_ACR_BYTE2_ADDRESS              ((uint32)0x40023C03)
-
-typedef struct
-{
-  __IO uint32 ACR;      /*!< FLASH access control register, Address offset: 0x00 */
-  __IO uint32 KEYR;     /*!< FLASH key register,            Address offset: 0x04 */
-  __IO uint32 OPTKEYR;  /*!< FLASH option key register,     Address offset: 0x08 */
-  __IO uint32 SR;       /*!< FLASH status register,         Address offset: 0x0C */
-  __IO uint32 CR;       /*!< FLASH control register,        Address offset: 0x10 */
-  __IO uint32 OPTCR;    /*!< FLASH option control register, Address offset: 0x14 */
-} FLASH_TypeDef;
-
-#define FLASH_R_BASE          (0x40023C00)
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define RESET 0
 
 //-----------------------------------------------------------------------------
 void InitMCO1()
@@ -232,7 +200,7 @@ void SetupClock72MHz()
 	while((RCC->CR & RCC_CR_PLLRDY) == 0);
 
 	/* Configure Flash prefetch, Instruction cache, Data cache and wait state */
-	FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_2WS;
+	flash_init(FLASH_ACR_LATENCY_2WS);
 
 	/* Select the main PLL as system clock source */
 	RCC->CFGR &= ~(RCC_CFGR_SW_MASK);
@@ -295,7 +263,7 @@ void SetupClock84MHz()
 	while((RCC->CR & RCC_CR_PLLRDY) == 0);
 
 	/* Configure Flash prefetch, Instruction cache, Data cache and wait state */
-	FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_3WS;
+	flash_init(FLASH_ACR_LATENCY_3WS);
 
 	/* Select the main PLL as system clock source */
 	RCC->CFGR &= ~(RCC_CFGR_SW_MASK);
@@ -358,7 +326,7 @@ void SetupClock96MHz()
 	while((RCC->CR & RCC_CR_PLLRDY) == 0);
 
 	/* Configure Flash prefetch, Instruction cache, Data cache and wait state */
-	FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_3WS;
+	flash_init(FLASH_ACR_LATENCY_3WS);
 
 	/* Select the main PLL as system clock source */
 	RCC->CFGR &= ~(RCC_CFGR_SW_MASK);
@@ -421,7 +389,7 @@ void SetupClock120MHz()
 	while((RCC->CR & RCC_CR_PLLRDY) == 0);
 
 	/* Configure Flash prefetch, Instruction cache, Data cache and wait state */
-	FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_3WS;
+	flash_init(FLASH_ACR_LATENCY_3WS);
 
 	/* Select the main PLL as system clock source */
 	RCC->CFGR &= (uint32_t)~(RCC_CFGR_SW_MASK);
@@ -494,7 +462,7 @@ void SetupClock168MHz()
 	while((RCC->CR & RCC_CR_PLLRDY) == 0);
 
 	/* Configure Flash prefetch, Instruction cache, Data cache and wait state */
-	FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
+	flash_init(FLASH_ACR_LATENCY_5WS);
 
 	/* Select the main PLL as system clock source */
 	RCC->CFGR &= (uint32_t)~(RCC_CFGR_SW_MASK);