GitHub - stevsvc/VHDL_Logic_Gates_Intro: Prepositional logic solver

Name		Name	Last commit message	Last commit date
Latest commit History 1 Commit
db		db
incremental_db		incremental_db
output_files		output_files
simulation/qsim		simulation/qsim
things		things
LogicalStep_ECE124_Lab1.tcl		LogicalStep_ECE124_Lab1.tcl
LogicalStep_Lab1.qpf		LogicalStep_Lab1.qpf
LogicalStep_Lab1_top.bdf		LogicalStep_Lab1_top.bdf
LogicalStep_Lab1_top.qsf		LogicalStep_Lab1_top.qsf
LogicalStep_Lab1_top.qws		LogicalStep_Lab1_top.qws
LogicalStep_Lab1_top_assignment_defaults.qdf		LogicalStep_Lab1_top_assignment_defaults.qdf
PolarityChangeControl.bdf		PolarityChangeControl.bdf
PolarityChangeControl.bsf		PolarityChangeControl.bsf
VHDL_gates.bsf		VHDL_gates.bsf
VHDL_gates.vhd		VHDL_gates.vhd
VHDL_gates.vhd.bak		VHDL_gates.vhd.bak
VHDL_newGates.bsf		VHDL_newGates.bsf
VHDL_newGates.vhd		VHDL_newGates.vhd
VHDL_newGates.vhd.bak		VHDL_newGates.vhd.bak
schem_gates.bdf		schem_gates.bdf
schem_gates.bsf		schem_gates.bsf