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@stffrdhrn
stffrdhrn committed Oct 12, 2015
1 parent 4aa79fa commit 96a71ed
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Showing 7 changed files with 118 additions and 18 deletions.
9 changes: 9 additions & 0 deletions Makefile
View file
@@ -0,0 +1,9 @@
# This doesnt really work, but I want to figure out how to do it
# so putting these helpers here.
vsim:
vlog bench/dacspi_tb.v
vlog rtl/dacspi.v
vsim -c -do "run; quit" dacspi_tb

vlib: work
vlib work
47 changes: 47 additions & 0 deletions bench/dacspi_tb.v
View file
@@ -0,0 +1,47 @@
module dacspi_tb();

reg rst_n, clk;
reg [15:0] wr_data;
reg wr;
wire spi_cs_n, spi_sclk, spi_sdout;

initial
begin
rst_n = 1;
clk = 0;
wr_data = 16'b1010_0110_1100_1101;
wr = 0;
end

always
#1 clk <= ~clk;

initial
begin
#4 rst_n = 0;
#4 rst_n = 1;

#4 wr = 1;
#4 wr = 0;

#16 if (spi_sdout != 1)
begin
$display("Expected spi_sdout to be high after 16 cycles");
$finish(1);
end

end

dacspi dacspi (
.wr_data(wr_data),
.wr(wr),

.spi_cs_n(spi_cs_n),
.spi_sclk(spi_sclk),
.spi_sdout(spi_sdout),

.clk(clk),
.rst_n(rst_n)
);

endmodule
2 changes: 1 addition & 1 deletion modules/pwm
Submodule pwm updated 1 files
+25 −31 rtl/pwmdac.v
18 changes: 17 additions & 1 deletion quartus/digi-recorder.qsf
View file
Expand Up @@ -142,7 +142,6 @@ set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[0] -t
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[5] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[25] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[18] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
set_global_assignment -name CDF_FILE output_files/Chain2.cdf
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[3] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[4] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[19] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
Expand All @@ -160,6 +159,9 @@ set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_location_assignment PIN_D3 -to GPIO_00
set_location_assignment PIN_C3 -to GPIO_01
set_location_assignment PIN_A3 -to GPIO_03
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to GPIO_01
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to GPIO_03
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to GPIO_07
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[6] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[8] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[9] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
Expand Down Expand Up @@ -233,5 +235,19 @@ set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[24] -
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[27] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[28] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[31] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to GPIO_00
set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 8
set_location_assignment PIN_M15 -to DIP[3]
set_location_assignment PIN_B9 -to DIP[2]
set_location_assignment PIN_T8 -to DIP[1]
set_location_assignment PIN_M1 -to DIP[0]
set_location_assignment PIN_L3 -to LED[7]
set_location_assignment PIN_B1 -to LED[6]
set_location_assignment PIN_F3 -to LED[5]
set_location_assignment PIN_D1 -to LED[4]
set_location_assignment PIN_A11 -to LED[3]
set_location_assignment PIN_B13 -to LED[2]
set_location_assignment PIN_A13 -to LED[1]
set_location_assignment PIN_A15 -to LED[0]
set_global_assignment -name SLD_FILE db/stp1_auto_stripped.stp
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
17 changes: 9 additions & 8 deletions rtl/dacspi.v
View file
Expand Up @@ -34,25 +34,26 @@ wire spi_sdout;
wire sdout_enabled;

assign sdout_enabled = count[4];
assign spi_sclk = clk;
assign spi_sclk = rst_n ? clk : 1'b0;
assign spi_sdout = sdout_enabled ? wr_data_r[15] : 1'b0;
assign spi_cs_n = ~count[4];
assign spi_cs_n = rst_n ? ~count[4] : 1'b1;

always @ (posedge clk)
always @ (negedge clk)
if (~rst_n)
begin
wr_data_r <= 16'd0;
count <= 5'd0;
end
else if (wr)
begin
wr_data_r <= wr_data;
count <= 5'b1_1111;
end
else if (sdout_enabled)
begin
count <= count - 1'b1;
wr_data_r <= {wr_data_r[14:0], 1'b0};
end
else if (wr)
begin
wr_data_r <= wr_data;
count <= 5'b1_1111;
end


endmodule
20 changes: 20 additions & 0 deletions rtl/drec_controller.v
View file
Expand Up @@ -29,6 +29,8 @@ module drec_controller (

ctl_play, ctl_rec, ctl_ack,

display,

clk, rst_n
);

Expand All @@ -52,6 +54,8 @@ input ctl_play;
input ctl_rec;
output ctl_ack;

output[7:0] display;

input clk;
input rst_n;

Expand All @@ -66,6 +70,8 @@ reg sdram_wr_enable;
reg sdram_rd_enable;
reg sdram_rd_data_ack;

reg [7:0] display;

reg ctl_ack;

/* Internals */
Expand Down Expand Up @@ -121,6 +127,20 @@ if (~rst_n)
else
ctl_ack <= (ctl_play | ctl_rec);


always @ (posedge clk)
if (~rst_n)
display <= 8'b0000_0000;
else
if ((state == RECORD) && sdram_addr_r[16])
display <= 8'b0001_1000;
else if (state == RECORD)
display <= 8'b0011_1100;
else if ((state == PLAY) && sdram_addr_r[16])
display <= 8'b0110_0110;
else if (state == PLAY)
display <= 8'b1001_1001;

/* Handle generating signle every 44000 hz */
always @ (posedge clk)
if (~rst_n)
Expand Down
23 changes: 15 additions & 8 deletions rtl/toplevel.v
View file
Expand Up @@ -22,11 +22,17 @@ module toplevel (
output ADC_OUT,


/* DIP SWITCHES */
input [3:0] DIP,

/* LEDS */
output [7:0] LED,

/* SPEAKER OUT */
output GPIO_07,
output GPIO_00,
output GPIO_01,
output GPIO_03,
output GPIO_07, // PWM OUT
output GPIO_00, // DAC SPI CS_N
output GPIO_01, // DAC SPI SCLK
output GPIO_03, // DAC SPI SOUT

input CLOCK_50,
input RESET // KEY 0
Expand All @@ -44,7 +50,6 @@ wire dbl_clck_rst_n;
wire [15:0] dac_data;
wire dac_enable;


// 0 0 0
// 0 1 0
// 1 0 1
Expand Down Expand Up @@ -98,6 +103,8 @@ drec_controller drec_controlleri (

.ctl_play(play_btn), .ctl_rec(rec_btn), .ctl_ack(btn_ack),

.display(LED),

.clk(clk1m1), .rst_n(RESET)
);

Expand Down Expand Up @@ -144,19 +151,19 @@ pwmdac daci (
.pwmout(GPIO_07),

.clk(pwmclk), /* 110Mhz 44000 x 250 x 10*/
.rst_n(RESET), // TODO it would be nice to only enable DAC during PLAY
.rst_n(RESET) // TODO it would be nice to only enable DAC during PLAY
);

dacspi dacspidi (
.wr_data({4'b0011, dac_data[11:0]}),
.wr_data({4'b0001, dac_data[11:0]}),
.wr(dac_enable),

.spi_cs_n(GPIO_00), // white
.spi_sclk(GPIO_01), // yellow
.spi_sdout(GPIO_03), // blue

.clk(clk1m1), /* 110Mhz 44000 x 250 x 10*/
.rst_n(RESET), // TODO it would be nice to only enable DAC during PLAY
.rst_n(RESET) // TODO it would be nice to only enable DAC during PLAY
);

wire [ 11:0] adc_dataout_12b;
Expand Down

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