update adc controller to be reading a signle value every 25 seconds

quartus/digi-recorder.qsf

@@ -61,8 +61,9 @@ set_global_assignment -name VERILOG_FILE ../rtl/drec_controller.v
 set_global_assignment -name VERILOG_FILE "../modules/sdram-controller/rtl/double_click.v"
 set_global_assignment -name VERILOG_FILE "../modules/sdram-controller/rtl/sdram_controller.v"
 set_global_assignment -name VERILOG_FILE ../modules/pwm/rtl/pwmdac.v
-set_global_assignment -name VERILOG_FILE "../modules/adc-interface/rtl/adc_interface.v"
 set_global_assignment -name VERILOG_FILE "../modules/sdram-controller/rtl/fifo.v"
 set_global_assignment -name SDC_FILE ../rtl/toplevel.sdc
 set_global_assignment -name QIP_FILE ../rtl/pll.qip
+set_global_assignment -name TEXT_FILE ../rtl/adcspi.txt
+set_global_assignment -name VERILOG_FILE ../rtl/adcspi.v
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

readme.md

@@ -1,3 +1,32 @@
 ## Digital Audio Recorder
 
-The heart is in fpga. Needs and ADC, speaker and sdram
+The heart is in fpga. Needs an ADC, speaker and sdram like those found in 
+De0 Nano. 
+
+## Compontent Timings
+
+### ADC
+Running at 1.1 Mhz
+(Top speed 3.2Mhz)
+
+ - 1 sample every 16 cycles
+ - 4 samples
+ - 44000 samples every second
+    16 x 4 x 44000 -> 2816000  - cannot implement on PLL
+             44100 -> 2822400  - cannot implement on PLL 
+
+
+
+### DAC - 110Mhz
+ (8-bit sample every 44000 hz)
+ 10 x 8-bit duty cycle (250) x 44000 -> 
+
+### Recorder Controller - 1.1Mhz
+ (sample every 25 cycles -> 44Hz)
+
+### Double Click        - 1.1Mhz
+
+### SDRAM                - 100Mhz
+
+# Todo
+ - clk and rst_n for all circuits

rtl/adcspi.v

@@ -0,0 +1,65 @@
+/**
+ * This ADC interface provides an serial to parallel interface for
+ * a ADC chip. 
+ * After reset the interface just loops collecting 1 reading from the
+ * ADC chip every 16 sclk cycles and stores them into its internal memory
+ * at one of 4 address spaces.  The data will be refreshed every 4x16 (64 cycles)
+ * So a consumer should be setup to read the data before its gone. 
+ */
+module adcspi  ( 
+  data,
+  cs_n, 
+  din,
+  dout,
+  clk, 
+  rst_n);
+
+output [11:0]  data;
+input          clk;
+input          din;
+output         dout;
+output         cs_n;
+input          rst_n;
+
+reg  [11:0]   data;
+
+reg  [4:0]    clk_count;
+reg  [11:0]   din_ff;
+reg  [11:0]   data_ram [0:2];
+
+/* Handle clock counting */
+always @ (posedge clk)
+  if (~rst_n) 
+    clk_count <= 5'd0;
+  else
+    if (clk_count == 5'd24)
+      clk_count <= clk_count + 1'b1;
+    else
+      clk_count <= 5'd0;
+
+/* if the count is over 16 then we are not transferring */      
+assign cs_n = clk_count[4];
+assign dout = clk_count[4]; // the address we are querying is always 00
+
+/* DeSerialize DIN, use a shift register to move DIN into a 12 bit register during
+ * clock cycles 4 -> 15
+ */
+always @ (posedge clk)
+  if (~rst_n)
+      din_ff <= 12'd0;
+  else
+    casez (clk_count)
+      5'b001??, 5'b01???: din_ff <= {din_ff[10:0], din};
+    endcase
+
+/* Return static ram on read interface
+ * Write shift register to static ram on first clock
+ */ 
+always @ (posedge clk) begin
+  if (~rst_n)
+     data <= 12'd0;
+  else if (clk_count == 5'b00000) 
+     data <= din_ff;
+end
+
+endmodule

rtl/toplevel.v

@@ -136,15 +136,14 @@ pwmdac daci (
 
 wire [ 11:0] adc_dataout_12b;
 assign       ADC_CLK = clk1m1;
-assign       ADC_CS_N = 1'b0;
 
-adc_interface  adc_interfacei (
-  .addr(2'b00), 
+adcspi adcspii (
   .data(adc_dataout_12b),
-  .din(ADC_OUT), 
-  .dout(ADC_IN),
-  .sclk(clk1m1), 
-  .rst(~RESET));
+  .cs_n(ADC_CS_N), 
+  .din(ADC_IN),
+  .dout(ADC_OUT),
+  .clk(clk1m1), 
+  .rst_n(RESET));
 
 assign DRAM_CLK = clk100;