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FAQ
Absolutely! My goal is to make a good Bitcoin miner for Zynq that allows anyone to take the design and do whatever they want with it! The end goal is to provide source files and steps on how implement it yourself.
Xilinx ISE/Vivado tools are great to work with, but are bad when it comes to source control management. It's easier to work with remote sources in the repo than it is to work with a project. Plus, I don't want to flood the GIT Repo with unnecessary files that get generated by the tools.
Look at the Readme.md and identify areas where I have marked TODO, or you can go and do whatever you want with the current source. As of 3/28/13, I am only working on the Vivado HLS C/C++ code for the SHA256 core (this needs to be optimized for Zynq to reduce LUT count and give it a good speed boost).
I sure will, but if you're not using a Zedboard, it will be useless to you. I recommend creating your own project and grabbing the source files and implement to your specific board design. UPDATE: I have decided to provide branches of each bitstream file for each released board.
I'm new to FPGAs (especially Zynq), and I want to use this project as a way to learn them. Will you provide detailed documentation on how to do things?
I'll be glad to provide detailed documentation for the project specifically, but for FPGA development, you're better off going to sites like www.fpga4fun.com and Xilinx's Youtube channel to learn more. FPGAs in general are not easy to learn or work with, so don't expect to pick it up overnight.
I haven't fully figured this out, but I am a big fan of Open Source and Open Source Hardware so I believe I will do one of two licenses: Beerware or Creative Commons.
I have other questions that are more specific towards you, what is the best way to get a hold of you?
The best and easiest way is to send me an email (which you can grab from my Github profile). I am very busy during the week, but I usually try to respond to inquiries as soon as I get them (or they will be buried in my email).
This is a tough question, but overall the answer will be, yes. The Zedboard is very basic with not many features utilizing the Zynq/ARM only pinouts. For the ZC702 or custom board designs, it should work overall as long as the pinouts are similar to the Zedboard. Generally, only RAM (DDR) and Ethernet pins will be utilized. Expect individual branches per board that is available.
If you want a bitstream generated for a custom board, please upload the valid placement and timing constraints (UCF/XDC) and I'll try to generate a bitstream for people to test.
I have a custom board, but I don't want to release it to the world and just hold on to it, can I still use your project (of course with my own modifications)?
Absolutely, but I do encourage you to open source your design. Open sourcing a design like this will do nothing but provide more traffic and will be beneficial for all parties.
As of right now, I have done a base implementation of the design, but it does not meet timing, but here are some basic data for those interested:
- Estimated: 4.79ns w/ .6ns jitter for the SHA256 core
- Estimated: 250mW for the PL (Programmable Logic) part of Zynq. I estimate that 5W will be what it draws when the Linux OS and arbiter are implemented.
- Semi-Confirmed: 5 Miners can be fit on the 7020 utilizing an AXI Interconnect to talk to the ARM (timing will never meet in this situation)
- Estimated: 350Mhash/s (this was back of the envelope calculation assuming each of the 5 miners were given a hash with an offset of a nanosecond. Basically, miner1 got it at 0ns, miner2 got it at 1ns, ... miner5 got it at 5ns)
This was of some debate, but since ASIC miners are destroying getwork with ease, I'd rather not run into the same issues; ergo, we are going to support the Stratum protocol. If anyone wants a getwork first, there will be a branch provided.