Merge #138

138: PWM support r=therealprof a=jonfin

Add PWM support based on the stm32f4xx_hal implementation. It is mostly a copy from stm32f4xx_hal with some modification.
Only change to stm32f4xx_hal: it uses the recommended order for setting the register from DM00042534

I did some testing based on a stm32f030c8 chip.

fixes #26

Co-authored-by: Jonas <jonas@finger-ling.de>

CHANGELOG.md

@@ -17,6 +17,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 ### Added
 
 - Add CAN bus abstraction based on the [bxcan] crate.
+- Add PWM output generation based on the timers.
 
 [bxcan]: https://crates.io/crates/bxcan
 

examples/pwm.rs

@@ -0,0 +1,38 @@
+#![deny(unsafe_code)]
+#![no_main]
+#![no_std]
+
+// Halt on panic
+use panic_halt as _;
+
+use cortex_m_rt::entry;
+
+use stm32f0xx_hal as hal;
+
+use hal::{pac, prelude::*, pwm};
+
+#[entry]
+fn main() -> ! {
+    if let Some(mut dp) = pac::Peripherals::take() {
+        // Set up the system clock.
+        let mut rcc = dp.RCC.configure().sysclk(8.mhz()).freeze(&mut dp.FLASH);
+
+        let gpioa = dp.GPIOA.split(&mut rcc);
+        let channels = cortex_m::interrupt::free(move |cs| {
+            (
+                gpioa.pa8.into_alternate_af2(cs),
+                gpioa.pa9.into_alternate_af2(cs),
+            )
+        });
+
+        let pwm = pwm::tim1(dp.TIM1, channels, &mut rcc, 20u32.khz());
+        let (mut ch1, _ch2) = pwm;
+        let max_duty = ch1.get_max_duty();
+        ch1.set_duty(max_duty / 2);
+        ch1.enable();
+    }
+
+    loop {
+        cortex_m::asm::nop();
+    }
+}

src/lib.rs

@@ -46,6 +46,8 @@ pub mod i2c;
 #[cfg(feature = "device-selected")]
 pub mod prelude;
 #[cfg(feature = "device-selected")]
+pub mod pwm;
+#[cfg(feature = "device-selected")]
 pub mod rcc;
 #[cfg(feature = "device-selected")]
 pub mod serial;