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Fix SPI initialization to be MSB first #60

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merged 3 commits into from
Mar 7, 2020
Merged

Fix SPI initialization to be MSB first #60

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50ec7c6
Fix SPI initialization to be MSB first
arlosi Feb 16, 2020
eed7cdd
Update changelog
arlosi Mar 5, 2020
bcd0f4a
Disable caching in CI
Sh3Rm4n Mar 7, 2020
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2 changes: 0 additions & 2 deletions .travis.yml
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Expand Up @@ -4,8 +4,6 @@ rust:
- stable
- nightly

cache: cargo

matrix:
allow_failures:
- rust: nightly
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3 changes: 3 additions & 0 deletions CHANGELOG.md
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Expand Up @@ -13,6 +13,9 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
- Implement blocking Write for UART
- Implement blocking Read for I2C

### Fixed
- Regression in v0.4.0 that set SPI to LSB-first ordering

## [v0.4.0] - 2019-12-27

### Added
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2 changes: 1 addition & 1 deletion src/spi.rs
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Expand Up @@ -182,7 +182,7 @@ macro_rules! hal {
w.spe()
.enabled()
.lsbfirst()
.lsbfirst()
.msbfirst()
.ssi()
.slave_not_selected()
.ssm()
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