Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Fix SPI initialization to be MSB first #60

Merged
merged 3 commits into from
Mar 7, 2020
Merged

Conversation

arlosi
Copy link
Contributor

@arlosi arlosi commented Feb 16, 2020

The comments indicate that the code is attempting to set the SPI order to MSB first, however it actually sets it to LSB first. Since most devices are MSB first, this is the correct choice.

Closes #59.

@arlosi
Copy link
Contributor Author

arlosi commented Feb 16, 2020

With master + this change, I can successfully communicate with two different SPI devices using an STM32F334

@Sh3Rm4n
Copy link
Member

Sh3Rm4n commented Mar 2, 2020

Thank you for this PR. Sorry for the delay, I was quite busy with work and uni stuff the last weeks.

It seems like I oversaw this, when I changed these lines. I briefly tested it today and it seems to fix the SPI issue. I will look into this PR this week :)

@Sh3Rm4n
Copy link
Member

Sh3Rm4n commented Mar 5, 2020

Okay I've confirmed that your fix is working.

Would be strange, if not 😅

I would be happy, if you added a note to the changelog. Something like:

# Fix

- Fixed regression ... spi was not correctly intialized as master

:)

@arlosi arlosi closed this Mar 5, 2020
@arlosi arlosi reopened this Mar 5, 2020
@Sh3Rm4n
Copy link
Member

Sh3Rm4n commented Mar 6, 2020

Thanks!

Meh travis timed out. Force pushing with --amend --no-edit or squashing the commits should retrigger travis.

I should look into fixing travis sometime, as two instances doing the sames is really not useful 😅

@Sh3Rm4n
Copy link
Member

Sh3Rm4n commented Mar 7, 2020

Thanks for force pushing. This sadly didn't help. The travis instance has a hard time initializing sscache. I'll look into fixing this.

For now this seems to time out the travis instance, so the build will not
succeed. Disable it for now until this issue is resolved.
@Sh3Rm4n Sh3Rm4n merged commit 13a66d4 into stm32-rs:master Mar 7, 2020
@Sh3Rm4n
Copy link
Member

Sh3Rm4n commented Mar 7, 2020

Disable caching in travis worked 🎉

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

Successfully merging this pull request may close these issues.

SPI initialization should set CR1.LSBFIRST bit to 'MSB first' by default
2 participants