[rtl] minor rtl code cleanups (#747)

stnolting · Dec 9, 2023 · 11df3a9 · 11df3a9
2 parents f63236c + c323645
commit 11df3a9
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diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -26,10 +26,11 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12
 * :warning: changes that might impact compatibility with previous versions
 * :lock: security/safety-related
 * :rocket: official release
-* Date format is _dd.mm.yyyy_
+* Date format is "dd.mm.yyyy"
 
 | Date | Version | Comment | Link |
 |:----:|:-------:|:--------|:----:|
+| 09.12.2023 | 1.9.2.4 | minor rtl code cleanups | [#747](https://github.com/stnolting/neorv32/pull/747) |
 | 09.12.2023 | 1.9.2.3 | refine behavior of CPU's sleep state & signal | [#746](https://github.com/stnolting/neorv32/pull/746) |
 | 05.12.2023 | 1.9.2.2 | reset `mstatus.mpp` to "machine-mode" | [#745](https://github.com/stnolting/neorv32/pull/745) |
 | 02.12.2023 | 1.9.2.1 | :sparkles: add RISC-V `Zicond` ISA extension (integer conditional operations) | [#743](https://github.com/stnolting/neorv32/pull/743) |

diff --git a/rtl/core/neorv32_cpu.vhd b/rtl/core/neorv32_cpu.vhd
@@ -42,36 +42,36 @@ use neorv32.neorv32_package.all;
 entity neorv32_cpu is
   generic (
     -- General --
-    HART_ID                      : std_ulogic_vector(31 downto 0); -- hardware thread ID
-    VENDOR_ID                    : std_ulogic_vector(31 downto 0); -- vendor's JEDEC ID
-    CPU_BOOT_ADDR                : std_ulogic_vector(31 downto 0); -- cpu boot address
-    CPU_DEBUG_PARK_ADDR          : std_ulogic_vector(31 downto 0); -- cpu debug mode parking loop entry address
-    CPU_DEBUG_EXC_ADDR           : std_ulogic_vector(31 downto 0); -- cpu debug mode exception entry address
+    HART_ID                    : std_ulogic_vector(31 downto 0); -- hardware thread ID
+    VENDOR_ID                  : std_ulogic_vector(31 downto 0); -- vendor's JEDEC ID
+    CPU_BOOT_ADDR              : std_ulogic_vector(31 downto 0); -- cpu boot address
+    CPU_DEBUG_PARK_ADDR        : std_ulogic_vector(31 downto 0); -- cpu debug mode parking loop entry address
+    CPU_DEBUG_EXC_ADDR         : std_ulogic_vector(31 downto 0); -- cpu debug mode exception entry address
     -- RISC-V CPU Extensions --
-    CPU_EXTENSION_RISCV_A        : boolean; -- implement atomic memory operations extension?
-    CPU_EXTENSION_RISCV_B        : boolean; -- implement bit-manipulation extension?
-    CPU_EXTENSION_RISCV_C        : boolean; -- implement compressed extension?
-    CPU_EXTENSION_RISCV_E        : boolean; -- implement embedded RF extension?
-    CPU_EXTENSION_RISCV_M        : boolean; -- implement mul/div extension?
-    CPU_EXTENSION_RISCV_U        : boolean; -- implement user mode extension?
-    CPU_EXTENSION_RISCV_Zfinx    : boolean; -- implement 32-bit floating-point extension (using INT reg!)
-    CPU_EXTENSION_RISCV_Zicntr   : boolean; -- implement base counters?
-    CPU_EXTENSION_RISCV_Zicond   : boolean; -- implement integer conditional operations?
-    CPU_EXTENSION_RISCV_Zihpm    : boolean; -- implement hardware performance monitors?
-    CPU_EXTENSION_RISCV_Zmmul    : boolean; -- implement multiply-only M sub-extension?
-    CPU_EXTENSION_RISCV_Zxcfu    : boolean; -- implement custom (instr.) functions unit?
-    CPU_EXTENSION_RISCV_Sdext    : boolean; -- implement external debug mode extension?
-    CPU_EXTENSION_RISCV_Sdtrig   : boolean; -- implement trigger module extension?
+    CPU_EXTENSION_RISCV_A      : boolean; -- implement atomic memory operations extension?
+    CPU_EXTENSION_RISCV_B      : boolean; -- implement bit-manipulation extension?
+    CPU_EXTENSION_RISCV_C      : boolean; -- implement compressed extension?
+    CPU_EXTENSION_RISCV_E      : boolean; -- implement embedded RF extension?
+    CPU_EXTENSION_RISCV_M      : boolean; -- implement mul/div extension?
+    CPU_EXTENSION_RISCV_U      : boolean; -- implement user mode extension?
+    CPU_EXTENSION_RISCV_Zfinx  : boolean; -- implement 32-bit floating-point extension (using INT reg!)
+    CPU_EXTENSION_RISCV_Zicntr : boolean; -- implement base counters?
+    CPU_EXTENSION_RISCV_Zicond : boolean; -- implement integer conditional operations?
+    CPU_EXTENSION_RISCV_Zihpm  : boolean; -- implement hardware performance monitors?
+    CPU_EXTENSION_RISCV_Zmmul  : boolean; -- implement multiply-only M sub-extension?
+    CPU_EXTENSION_RISCV_Zxcfu  : boolean; -- implement custom (instr.) functions unit?
+    CPU_EXTENSION_RISCV_Sdext  : boolean; -- implement external debug mode extension?
+    CPU_EXTENSION_RISCV_Sdtrig : boolean; -- implement trigger module extension?
     -- Tuning Options --
-    FAST_MUL_EN                  : boolean; -- use DSPs for M extension's multiplier
-    FAST_SHIFT_EN                : boolean; -- use barrel shifter for shift operations
-    REGFILE_HW_RST               : boolean; -- implement full hardware reset for register file
+    FAST_MUL_EN                : boolean; -- use DSPs for M extension's multiplier
+    FAST_SHIFT_EN              : boolean; -- use barrel shifter for shift operations
+    REGFILE_HW_RST             : boolean; -- implement full hardware reset for register file
     -- Physical Memory Protection (PMP) --
-    PMP_NUM_REGIONS              : natural range 0 to 16; -- number of regions (0..16)
-    PMP_MIN_GRANULARITY          : natural; -- minimal region granularity in bytes, has to be a power of 2, min 4 bytes
+    PMP_NUM_REGIONS            : natural range 0 to 16; -- number of regions (0..16)
+    PMP_MIN_GRANULARITY        : natural; -- minimal region granularity in bytes, has to be a power of 2, min 4 bytes
     -- Hardware Performance Monitors (HPM) --
-    HPM_NUM_CNTS                 : natural range 0 to 13; -- number of implemented HPM counters (0..13)
-    HPM_CNT_WIDTH                : natural range 0 to 64  -- total size of HPM counters (0..64)
+    HPM_NUM_CNTS               : natural range 0 to 13; -- number of implemented HPM counters (0..13)
+    HPM_CNT_WIDTH              : natural range 0 to 64  -- total size of HPM counters (0..64)
   );
   port (
     -- global control --
@@ -114,10 +114,8 @@ architecture neorv32_cpu_rtl of neorv32_cpu is
   -- local signals --
   signal ctrl         : ctrl_bus_t; -- main control bus
   signal imm          : std_ulogic_vector(XLEN-1 downto 0); -- immediate
-  signal rs1          : std_ulogic_vector(XLEN-1 downto 0); -- source register 1
-  signal rs2          : std_ulogic_vector(XLEN-1 downto 0); -- source register 2
-  signal rs3          : std_ulogic_vector(XLEN-1 downto 0); -- source register 3
-  signal rs4          : std_ulogic_vector(XLEN-1 downto 0); -- source register 4
+  signal rs1, rs2     : std_ulogic_vector(XLEN-1 downto 0); -- source register 1,2
+  signal rs3, rs4     : std_ulogic_vector(XLEN-1 downto 0); -- source register 3,4
   signal alu_res      : std_ulogic_vector(XLEN-1 downto 0); -- alu result
   signal alu_add      : std_ulogic_vector(XLEN-1 downto 0); -- alu address result
   signal alu_cmp      : std_ulogic_vector(1 downto 0); -- comparator result
@@ -141,8 +139,7 @@ begin
   -- Sanity Checks --------------------------------------------------------------------------
   -- -------------------------------------------------------------------------------------------
   -- CPU ISA configuration --
-  assert false report
-    "[NEORV32] CPU ISA: rv32" &
+  assert false report "[NEORV32] CPU ISA: rv32" &
     cond_sel_string_f(CPU_EXTENSION_RISCV_E,      "e",         "i") &
     cond_sel_string_f(CPU_EXTENSION_RISCV_M,      "m",         "" ) &
     cond_sel_string_f(CPU_EXTENSION_RISCV_A,      "a",         "" ) &
@@ -163,51 +160,49 @@ begin
     severity note;
 
   -- CPU tuning options --
-  assert false report
-    "[NEORV32] CPU tuning options: " &
+  assert false report "[NEORV32] CPU tuning options: " &
     cond_sel_string_f(FAST_MUL_EN,    "fast_mul ",   "") &
     cond_sel_string_f(FAST_SHIFT_EN,  "fast_shift ", "" ) &
     cond_sel_string_f(REGFILE_HW_RST, "rf_hw_rst",   "" )
     severity note;
 
   -- simulation notifier --
-  assert not (is_simulation_c = true) report
-    "[NEORV32] Assuming this is a simulation." severity warning;
+  assert not (is_simulation_c = true) report "[NEORV32] Assuming this is a simulation." severity warning;
 
 
   -- Control Unit ---------------------------------------------------------------------------
   -- -------------------------------------------------------------------------------------------
   neorv32_cpu_control_inst: entity neorv32.neorv32_cpu_control
   generic map (
     -- General --
-    HART_ID                    => HART_ID,                      -- hardware thread ID
-    VENDOR_ID                  => VENDOR_ID,                    -- vendor's JEDEC ID
-    CPU_BOOT_ADDR              => CPU_BOOT_ADDR,                -- cpu boot address
-    CPU_DEBUG_PARK_ADDR        => CPU_DEBUG_PARK_ADDR,          -- cpu debug mode parking loop entry address
-    CPU_DEBUG_EXC_ADDR         => CPU_DEBUG_EXC_ADDR,           -- cpu debug mode exception entry address
+    HART_ID                    => HART_ID,                    -- hardware thread ID
+    VENDOR_ID                  => VENDOR_ID,                  -- vendor's JEDEC ID
+    CPU_BOOT_ADDR              => CPU_BOOT_ADDR,              -- cpu boot address
+    CPU_DEBUG_PARK_ADDR        => CPU_DEBUG_PARK_ADDR,        -- cpu debug mode parking loop entry address
+    CPU_DEBUG_EXC_ADDR         => CPU_DEBUG_EXC_ADDR,         -- cpu debug mode exception entry address
     -- RISC-V CPU Extensions --
-    CPU_EXTENSION_RISCV_A      => CPU_EXTENSION_RISCV_A,        -- implement atomic memory operations extension?
-    CPU_EXTENSION_RISCV_B      => CPU_EXTENSION_RISCV_B,        -- implement bit-manipulation extension?
-    CPU_EXTENSION_RISCV_C      => CPU_EXTENSION_RISCV_C,        -- implement compressed extension?
-    CPU_EXTENSION_RISCV_E      => CPU_EXTENSION_RISCV_E,        -- implement embedded RF extension?
-    CPU_EXTENSION_RISCV_M      => CPU_EXTENSION_RISCV_M,        -- implement mul/div extension?
-    CPU_EXTENSION_RISCV_U      => CPU_EXTENSION_RISCV_U,        -- implement user mode extension?
-    CPU_EXTENSION_RISCV_Zfinx  => CPU_EXTENSION_RISCV_Zfinx,    -- implement 32-bit floating-point extension (using INT reg!)
-    CPU_EXTENSION_RISCV_Zicntr => CPU_EXTENSION_RISCV_Zicntr,   -- implement base counters?
-    CPU_EXTENSION_RISCV_Zicond => CPU_EXTENSION_RISCV_Zicond,   -- implement integer conditional operations?
-    CPU_EXTENSION_RISCV_Zihpm  => CPU_EXTENSION_RISCV_Zihpm,    -- implement hardware performance monitors?
-    CPU_EXTENSION_RISCV_Zmmul  => CPU_EXTENSION_RISCV_Zmmul,    -- implement multiply-only M sub-extension?
-    CPU_EXTENSION_RISCV_Zxcfu  => CPU_EXTENSION_RISCV_Zxcfu,    -- implement custom (instr.) functions unit?
-    CPU_EXTENSION_RISCV_Sdext  => CPU_EXTENSION_RISCV_Sdext,    -- implement external debug mode extension?
-    CPU_EXTENSION_RISCV_Sdtrig => CPU_EXTENSION_RISCV_Sdtrig,   -- implement trigger module extension?
-    CPU_EXTENSION_RISCV_Smpmp  => pmp_enable_c,                 -- implement physical memory protection?
+    CPU_EXTENSION_RISCV_A      => CPU_EXTENSION_RISCV_A,      -- implement atomic memory operations extension?
+    CPU_EXTENSION_RISCV_B      => CPU_EXTENSION_RISCV_B,      -- implement bit-manipulation extension?
+    CPU_EXTENSION_RISCV_C      => CPU_EXTENSION_RISCV_C,      -- implement compressed extension?
+    CPU_EXTENSION_RISCV_E      => CPU_EXTENSION_RISCV_E,      -- implement embedded RF extension?
+    CPU_EXTENSION_RISCV_M      => CPU_EXTENSION_RISCV_M,      -- implement mul/div extension?
+    CPU_EXTENSION_RISCV_U      => CPU_EXTENSION_RISCV_U,      -- implement user mode extension?
+    CPU_EXTENSION_RISCV_Zfinx  => CPU_EXTENSION_RISCV_Zfinx,  -- implement 32-bit floating-point extension (using INT reg!)
+    CPU_EXTENSION_RISCV_Zicntr => CPU_EXTENSION_RISCV_Zicntr, -- implement base counters?
+    CPU_EXTENSION_RISCV_Zicond => CPU_EXTENSION_RISCV_Zicond, -- implement integer conditional operations?
+    CPU_EXTENSION_RISCV_Zihpm  => CPU_EXTENSION_RISCV_Zihpm,  -- implement hardware performance monitors?
+    CPU_EXTENSION_RISCV_Zmmul  => CPU_EXTENSION_RISCV_Zmmul,  -- implement multiply-only M sub-extension?
+    CPU_EXTENSION_RISCV_Zxcfu  => CPU_EXTENSION_RISCV_Zxcfu,  -- implement custom (instr.) functions unit?
+    CPU_EXTENSION_RISCV_Sdext  => CPU_EXTENSION_RISCV_Sdext,  -- implement external debug mode extension?
+    CPU_EXTENSION_RISCV_Sdtrig => CPU_EXTENSION_RISCV_Sdtrig, -- implement trigger module extension?
+    CPU_EXTENSION_RISCV_Smpmp  => pmp_enable_c,               -- implement physical memory protection?
     -- Tuning Options --
-    FAST_MUL_EN                => FAST_MUL_EN,                  -- use DSPs for M extension's multiplier
-    FAST_SHIFT_EN              => FAST_SHIFT_EN,                -- use barrel shifter for shift operations
-    REGFILE_HW_RST             => REGFILE_HW_RST,               -- implement full hardware reset for register file
+    FAST_MUL_EN                => FAST_MUL_EN,                -- use DSPs for M extension's multiplier
+    FAST_SHIFT_EN              => FAST_SHIFT_EN,              -- use barrel shifter for shift operations
+    REGFILE_HW_RST             => REGFILE_HW_RST,             -- implement full hardware reset for register file
     -- Hardware Performance Monitors (HPM) --
-    HPM_NUM_CNTS               => HPM_NUM_CNTS,                 -- number of implemented HPM counters (0..13)
-    HPM_CNT_WIDTH              => HPM_CNT_WIDTH                 -- total size of HPM counters
+    HPM_NUM_CNTS               => HPM_NUM_CNTS,               -- number of implemented HPM counters (0..13)
+    HPM_CNT_WIDTH              => HPM_CNT_WIDTH               -- total size of HPM counters
   )
   port map (
     -- global control --
@@ -363,7 +358,7 @@ begin
   -- Physical Memory Protection -------------------------------------------------------------
   -- -------------------------------------------------------------------------------------------
   pmp_inst_true:
-  if (pmp_enable_c = true) generate
+  if pmp_enable_c generate
     neorv32_cpu_pmp_inst: entity neorv32.neorv32_cpu_pmp
     generic map (
       NUM_REGIONS => PMP_NUM_REGIONS,    -- number of regions (0..16)
@@ -389,7 +384,7 @@ begin
   end generate;
 
   pmp_inst_false:
-  if (pmp_enable_c = false) generate
+  if not pmp_enable_c generate
     xcsr_rdata_pmp <= (others => '0');
     pmp_ex_fault   <= '0';
     pmp_rw_fault   <= '0';