[docs] minor edits

stnolting · Jun 30, 2023 · 60d1db1 · 60d1db1
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Showing 3 changed files with 5 additions and 3 deletions.
diff --git a/docs/datasheet/cpu.adoc b/docs/datasheet/cpu.adoc
@@ -298,7 +298,7 @@ The `I` ISA extensions is the base RISC-V integer ISA that is always enabled.
 | ALU shifts    | `sll[i]` `srl[i]` `sra[i]`                                                | 3 + 1..32; FAST_SHIFT: 4
 | Branches      | `beq` `bne` `blt` `bge` `bltu` `bgeu`                                     | taken: 6; not taken: 3
 | Jump/call     | `jal[r]`                                                                  | 6
-| Load/store    | `lb` `lh` `lw` `lbu` `lhu` `sb` `sh` `sw`                                 | 4
+| Load/store    | `lb` `lh` `lw` `lbu` `lhu` `sb` `sh` `sw`                                 | 5
 | System        | `ecall` `ebreak`                                                          | 3
 | Data fence    | `fence`                                                                   | 5
 | Illegal inst. | -                                                                         | 3

diff --git a/docs/datasheet/soc_dcache.adoc b/docs/datasheet/soc_dcache.adoc
@@ -31,7 +31,8 @@ when they are mapped to upper-most 256 MB address page (see section <<_address_s
 .Caching Internal Memories
 [NOTE]
 The data cache is intended to accelerate data access to **processor-external** memories
-(via the external bus interface or via the XIP module).
+(via the external bus interface or via the XIP module). The cache(s) should not be implemented
+when using only processor-internal data and instruction memories.
 
 .Manual Cache Clear/Reload
 [NOTE]

diff --git a/docs/datasheet/soc_icache.adoc b/docs/datasheet/soc_icache.adoc
@@ -29,7 +29,8 @@ used) is used.
 .Caching Internal Memories
 [NOTE]
 The instruction cache is intended to accelerate instruction fetches from **processor-external** memories
-(via the external bus interface or via the XIP module).
+(via the external bus interface or via the XIP module). The cache(s) should not be implemented
+when using only processor-internal data and instruction memories.
 
 .Manual Cache Clear/Reload
 [NOTE]