[CPU] area and timing optimization; closing further illegal instruction holes #293
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moved memory data registers and optimized data alignment logic: ~20% less hardware required due to better logic->LUT combining
added malformed "mret" (incorrect opcode) that will crash the system if any part of it gets executed
use malformed "mret" for testing and also check for unintended side effects
stnolting
changed the title
* reduced hardware costs (smaller logic) * shortened critical path (branch logic); ~10% higher f_max * closed further illegal instruction holes
fixed rare bug: malformed instruction word (with opcode from the compressed instructions space) caused computation of wrong return address if C extension is disabled
* further optimizations * added logic to avoid side-effects of illegal xret instructions
achieving 130MHz on Intel Cyclone IV!
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馃搱 This PR improves the overall efficiency of the CPU: the logic optimizations from this PR reduce the area costs of the CPU (~8% less) while also shortening the CPU's critical path (~12% higher f_max).
馃敀 Furthermore, this PR closes further illegal instruction holes (illegal instruction words that where not correctly detected or that caused side effects even if identified as "illegal").
馃悰 This PR also fixes a rare bug in the core of the NEORV32 runtime-environment (RTE): if the C-extensions is disabled, a malformed instruction word that uses an opcode from the RVC (compressed) instruction space would cause the computation of an incorrect return address.