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馃悰 [rtl] cycle & instret bug fix, wishbone.we bug fix; minor rtl updates #367

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merged 11 commits into from Jul 15, 2022
Merged

馃悰 [rtl] cycle & instret bug fix, wishbone.we bug fix; minor rtl updates #367

merged 11 commits into from Jul 15, 2022

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@stnolting stnolting commented Jul 15, 2022 •
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  • 馃悰 fixes a bug that permanently stops [m]cycle[h] and [m]instret[h] counter if no HPM counters are implemented (HPM_NUM_CNTS = 0)
  • 馃悰 fix bug in WISHBONE.WE signal (when ASYNC_TX mode enabled): signal was high for 1 cycle even if a read transfers (we = low) was triggered (@ Processor wrapper for LiteX integration聽#350)
  • hardwired dcsr.mprven to 1: mstatus.mprv is also evaluated when in debug mode
  • CFS can now check the current CPU privilege mode (to optionally constrain access/features to privileged software only)
  • minor rtl clean-ups

@stnolting stnolting added bug Something isn't working HW hardware-related labels Jul 15, 2022
@stnolting stnolting self-assigned this Jul 15, 2022
@stnolting stnolting changed the title 馃悰 [rtl] cycle and instret bug fix; minor rtl updates 馃悰 [rtl] cycle & instret bug fix, wishbone.we bug fix; minor rtl updates Jul 15, 2022
@stnolting stnolting marked this pull request as ready for review July 15, 2022 10:51
@stnolting stnolting merged commit 1d223bb into main Jul 15, 2022
@stnolting stnolting deleted the rtl_updates branch July 15, 2022 10:58
@stnolting stnolting mentioned this pull request Jul 15, 2022
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