stnolting · stnolting · Oct 30, 2023 · Oct 29, 2023 · Oct 29, 2023 · Oct 29, 2023
diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -32,6 +32,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12
 
 | Date (*dd.mm.yyyy*) | Version | Comment |
 |:-------------------:|:-------:|:--------|
+| 30.10.2023 | 1.9.0.5 | minor rtl cleanups and code beautification; [#718](https://github.com/stnolting/neorv32/pull/718) |
 | 28.10.2023 | 1.9.0.4 | :warning: :sparkles: move FreeRTOS port and demo to a new repository: https://github.com/stnolting/neorv32-freertos; [#716](https://github.com/stnolting/neorv32/pull/716) |
 | 18.10.2023 | 1.9.0.3 | :warning: remove top's `CPU_EXTENSION_RISCV_Zifencei` generic - `Zifencei` ISA extension is now always enabled; [#709](https://github.com/stnolting/neorv32/pull/709) |
 | 16.10.2023 | 1.9.0.2 | minor CPU control cleanups and optimizations (branch system); [#707](https://github.com/stnolting/neorv32/pull/707) |

diff --git a/rtl/core/mem/neorv32_dmem.default.vhd b/rtl/core/mem/neorv32_dmem.default.vhd
@@ -49,7 +49,7 @@ architecture neorv32_dmem_rtl of neorv32_dmem is
   -- -------------------------------------------------------------------------------------------------------------- --
   -- The memory (RAM) is built from 4 individual byte-wide memories b0..b3, since some synthesis tools have         --
   -- problems with 32-bit memories that provide dedicated byte-enable signals AND/OR with multi-dimensional arrays. --
-  -- [NOTE] Read-during-write behavior is irrelevant as read and write access are mutually exclusive.               --
+  -- [NOTE] Read-during-write behavior is irrelevant as read and write accesses are mutually exclusive.             --
   -- -------------------------------------------------------------------------------------------------------------- --
 
   -- RAM - not initialized at all --

diff --git a/rtl/core/mem/neorv32_dmem.legacy.vhd b/rtl/core/mem/neorv32_dmem.legacy.vhd
@@ -50,7 +50,7 @@ architecture neorv32_dmem_rtl of neorv32_dmem is
   -- -------------------------------------------------------------------------------------------------------------- --
   -- The memory (RAM) is built from 4 individual byte-wide memories b0..b3, since some synthesis tools have         --
   -- problems with 32-bit memories that provide dedicated byte-enable signals AND/OR with multi-dimensional arrays. --
-  -- [NOTE] Read-during-write behavior is irrelevant as read and write access are mutually exclusive.               --
+  -- [NOTE] Read-during-write behavior is irrelevant as read and write accesses are mutually exclusive.             --
   -- -------------------------------------------------------------------------------------------------------------- --
 
   -- RAM - not initialized at all --

diff --git a/rtl/core/mem/neorv32_imem.default.vhd b/rtl/core/mem/neorv32_imem.default.vhd
@@ -66,7 +66,7 @@ architecture neorv32_imem_rtl of neorv32_imem is
   -- -------------------------------------------------------------------------------------------------------------- --
   -- The memory (RAM) is built from 4 individual byte-wide memories b0..b3, since some synthesis tools have         --
   -- problems with 32-bit memories that provide dedicated byte-enable signals AND/OR with multi-dimensional arrays. --
-  -- [NOTE] Read-during-write behavior is irrelevant as read and write access are mutually exclusive.               --
+  -- [NOTE] Read-during-write behavior is irrelevant as read and write accesses are mutually exclusive.             --
   -- -------------------------------------------------------------------------------------------------------------- --
 
   -- RAM - not initialized at all --

diff --git a/rtl/core/mem/neorv32_imem.legacy.vhd b/rtl/core/mem/neorv32_imem.legacy.vhd
@@ -67,7 +67,7 @@ architecture neorv32_imem_rtl of neorv32_imem is
   -- -------------------------------------------------------------------------------------------------------------- --
   -- The memory (RAM) is built from 4 individual byte-wide memories b0..b3, since some synthesis tools have         --
   -- problems with 32-bit memories that provide dedicated byte-enable signals AND/OR with multi-dimensional arrays. --
-  -- [NOTE] Read-during-write behavior is irrelevant as read and write access are mutually exclusive.               --
+  -- [NOTE] Read-during-write behavior is irrelevant as read and write accesses are mutually exclusive.             --
   -- -------------------------------------------------------------------------------------------------------------- --
 
   -- RAM - not initialized at all --

diff --git a/rtl/core/neorv32_cpu.vhd b/rtl/core/neorv32_cpu.vhd
@@ -138,43 +138,31 @@ begin
 
   -- Sanity Checks --------------------------------------------------------------------------
   -- -------------------------------------------------------------------------------------------
-  -- say hello --
-  assert false report
-    "The NEORV32 RISC-V Processor, Version 0x" & to_hstring32_f(hw_version_c) & " - github.com/stnolting/neorv32" severity note;
-
   -- CPU ISA configuration --
   assert false report
     "NEORV32 CPU Configuration: RV32" &
-    cond_sel_string_f(CPU_EXTENSION_RISCV_E,      "E", "I") &
-    cond_sel_string_f(CPU_EXTENSION_RISCV_M,      "M", "") &
-    cond_sel_string_f(CPU_EXTENSION_RISCV_A,      "A", "") &
-    cond_sel_string_f(CPU_EXTENSION_RISCV_C,      "C", "") &
-    cond_sel_string_f(CPU_EXTENSION_RISCV_B,      "B", "") &
-    cond_sel_string_f(CPU_EXTENSION_RISCV_U,      "U", "") &
-    cond_sel_string_f(true,                       "_Zicsr", "") & -- always enabled
-    cond_sel_string_f(CPU_EXTENSION_RISCV_Zicntr, "_Zicntr", "") &
-    cond_sel_string_f(true,                       "_Zifencei", "") & -- always enabled
-    cond_sel_string_f(CPU_EXTENSION_RISCV_Zfinx,  "_Zfinx", "") &
-    cond_sel_string_f(CPU_EXTENSION_RISCV_Zihpm,  "_Zihpm", "") &
-    cond_sel_string_f(CPU_EXTENSION_RISCV_Zmmul,  "_Zmmul", "") &
-    cond_sel_string_f(CPU_EXTENSION_RISCV_Zxcfu,  "_Zxcfu", "") &
-    cond_sel_string_f(CPU_EXTENSION_RISCV_Sdext,  "_Sdext", "") &
-    cond_sel_string_f(CPU_EXTENSION_RISCV_Sdtrig, "_Sdtrig", "") &
-    cond_sel_string_f(pmp_enable_c,               "_Smpmp", "")
+    cond_sel_string_f(CPU_EXTENSION_RISCV_E,      "E",         "I") &
+    cond_sel_string_f(CPU_EXTENSION_RISCV_M,      "M",         "" ) &
+    cond_sel_string_f(CPU_EXTENSION_RISCV_A,      "A",         "" ) &
+    cond_sel_string_f(CPU_EXTENSION_RISCV_C,      "C",         "" ) &
+    cond_sel_string_f(CPU_EXTENSION_RISCV_B,      "B",         "" ) &
+    cond_sel_string_f(CPU_EXTENSION_RISCV_U,      "U",         "" ) &
+    cond_sel_string_f(true,                       "_Zicsr",    "" ) & -- always enabled
+    cond_sel_string_f(CPU_EXTENSION_RISCV_Zicntr, "_Zicntr",   "" ) &
+    cond_sel_string_f(true,                       "_Zifencei", "" ) & -- always enabled
+    cond_sel_string_f(CPU_EXTENSION_RISCV_Zfinx,  "_Zfinx",    "" ) &
+    cond_sel_string_f(CPU_EXTENSION_RISCV_Zihpm,  "_Zihpm",    "" ) &
+    cond_sel_string_f(CPU_EXTENSION_RISCV_Zmmul,  "_Zmmul",    "" ) &
+    cond_sel_string_f(CPU_EXTENSION_RISCV_Zxcfu,  "_Zxcfu",    "" ) &
+    cond_sel_string_f(CPU_EXTENSION_RISCV_Sdext,  "_Sdext",    "" ) &
+    cond_sel_string_f(CPU_EXTENSION_RISCV_Sdtrig, "_Sdtrig",   "" ) &
+    cond_sel_string_f(pmp_enable_c,               "_Smpmp",    "" )
     severity note;
 
   -- simulation notifier --
   assert not (is_simulation_c = true) report
     "NEORV32 CPU WARNING! Assuming this is a simulation." severity warning;
 
-  -- CPU boot address --
-  assert not (CPU_BOOT_ADDR(1 downto 0) /= "00") report
-    "NEORV32 CPU CONFIG ERROR! <CPU_BOOT_ADDR> has to be 32-bit aligned." severity error;
-
-  -- Hardware multiplier extensions --
-  assert not ((CPU_EXTENSION_RISCV_Zmmul = true) and (CPU_EXTENSION_RISCV_M = true)) report
-    "NEORV32 CPU CONFIG ERROR! <M> and <Zmmul> extensions cannot co-exist!" severity error;
-
 
   -- Control Unit ---------------------------------------------------------------------------
   -- -------------------------------------------------------------------------------------------
@@ -280,7 +268,7 @@ begin
     alu_i  => alu_res,   -- ALU result
     mem_i  => mem_rdata, -- memory read data
     csr_i  => csr_rdata, -- CSR read data
-    pc2_i  => next_pc,   -- next PC
+    npc_i  => next_pc,   -- next PC
     -- data output --
     rs1_o  => rs1,       -- rs1
     rs2_o  => rs2,       -- rs2
@@ -388,8 +376,8 @@ begin
   pmp_inst_false:
   if (pmp_enable_c = false) generate
     xcsr_rdata_pmp <= (others => '0');
-    pmp_ex_fault <= '0';
-    pmp_rw_fault <= '0';
+    pmp_ex_fault   <= '0';
+    pmp_rw_fault   <= '0';
   end generate;
 
 

diff --git a/rtl/core/neorv32_cpu_alu.vhd b/rtl/core/neorv32_cpu_alu.vhd
@@ -143,9 +143,9 @@ begin
       when alu_op_slt_c  => res_o(XLEN-1 downto 1) <= (others => '0');
                             res_o(0) <= addsub_res(addsub_res'left); -- carry/borrow
       when alu_op_movb_c => res_o <= opb;
-      when alu_op_xor_c  => res_o <= rs1_i xor opb; -- only rs1 is required for logic ops (opa would also contain pc)
-      when alu_op_or_c   => res_o <= rs1_i or  opb;
-      when alu_op_and_c  => res_o <= rs1_i and opb;
+      when alu_op_xor_c  => res_o <= opb xor rs1_i;
+      when alu_op_or_c   => res_o <= opb or  rs1_i;
+      when alu_op_and_c  => res_o <= opb and rs1_i;
       when others        => res_o <= addsub_res(XLEN-1 downto 0); -- don't care
     end case;
   end process alu_core;

diff --git a/rtl/core/neorv32_cpu_control.vhd b/rtl/core/neorv32_cpu_control.vhd
@@ -344,7 +344,7 @@ architecture neorv32_cpu_control_rtl of neorv32_cpu_control is
   -- hardware trigger module --
   signal hw_trigger_fire : std_ulogic;
 
-  -- CSR read-back data helpers --
+  -- CSR read-back helpers --
   signal csr_rdata, xcsr_rdata : std_ulogic_vector(XLEN-1 downto 0);
 
 begin
@@ -367,7 +367,7 @@ begin
       -- previous state (for HPMs only) --
       fetch_engine.state_prev <= fetch_engine.state;
 
-      -- restart request buffer --
+      -- restart request --
       if (fetch_engine.state = IF_RESTART) then -- restart done
         fetch_engine.restart <= '0';
       else -- buffer request
@@ -595,7 +595,8 @@ begin
           else
             NULL;
           end if;
-        when others => NULL;
+        when others =>
+          NULL;
       end case;
     end if;
   end process imm_gen;
@@ -1004,7 +1005,7 @@ begin
         execute_engine.state_nxt <= DISPATCH;
         -- house keeping: use this state to (re-)initialize the register file's x0/zero register --
         if (reset_x0_c = true) then -- if x0 is a "real" register that has to be initialized to zero
-          ctrl_nxt.rf_mux     <= rf_mux_csr_c; -- this will return 0 since csr.re_nxt has not been set
+          ctrl_nxt.rf_mux     <= rf_mux_csr_c; -- this will return 0 since csr.re_nxt is zero
           ctrl_nxt.rf_zero_we <= '1'; -- allow/force write access to x0
         end if;
 
@@ -1653,7 +1654,7 @@ begin
             if (csr.wdata(1 downto 0) = "01") then
               csr.mtvec <= csr.wdata(XLEN-1 downto 7) & "00000" & "01"; -- mtvec.MODE=1 (vectored)
             else
-              csr.mtvec <= csr.wdata(XLEN-1 downto 2) & "00";           -- mtvec.MODE=0 (direct)
+              csr.mtvec <= csr.wdata(XLEN-1 downto 2) & "00"; -- mtvec.MODE=0 (direct)
             end if;
 
           when csr_mcounteren_c => -- machine counter access enable
@@ -2092,10 +2093,11 @@ begin
       csr.re    <= '0';
       csr.rdata <= (others => '0');
     elsif rising_edge(clk_i) then
-      csr.re    <= csr.re_nxt;
-      csr.rdata <= (others => '0'); -- output zero if no valid CSR access operation
+      csr.re <= csr.re_nxt;
       if (csr.re = '1') then
         csr.rdata <= csr_rdata or xcsr_rdata;
+      else
+        csr.rdata <= (others => '0'); -- output zero if no valid CSR read access operation
       end if;
     end if;
   end process csr_read_reg;
@@ -2299,12 +2301,12 @@ begin
     elsif rising_edge(clk_i) then
       if (CPU_EXTENSION_RISCV_Sdext = true) then
         debug_ctrl.ext_halt_req <= db_halt_req_i; -- external halt request (from Debug Module)
-        if (debug_ctrl.running = '0') then -- debug mode OFFLINE - waiting for entry event
-          if (trap_ctrl.env_enter = '1') and (trap_ctrl.cause(5) = '1') then
+        if (debug_ctrl.running = '0') then -- debug mode OFFLINE
+          if (trap_ctrl.env_enter = '1') and (trap_ctrl.cause(5) = '1') then -- waiting for entry event
             debug_ctrl.running <= '1';
           end if;
-        else -- debug mode ONLINE - waiting for exit event
-          if (trap_ctrl.env_exit = '1') then
+        else -- debug mode ONLINE
+          if (trap_ctrl.env_exit = '1') then -- waiting for exit event
             debug_ctrl.running <= '0';
           end if;
         end if;
@@ -2329,7 +2331,7 @@ begin
   csr.dcsr_rd(31 downto 28) <= "0100"; -- xdebugver: external debug support compatible to spec. version 1.0
   csr.dcsr_rd(27 downto 16) <= (others => '0'); -- reserved
   csr.dcsr_rd(15)           <= csr.dcsr_ebreakm; -- ebreakm: what happens on ebreak in m-mode? (normal trap OR debug-enter)
-  csr.dcsr_rd(14)           <= '0'; -- ebreakh: hypervisor mode not implemented
+  csr.dcsr_rd(14)           <= '0'; -- reserved
   csr.dcsr_rd(13)           <= '0'; -- ebreaks: supervisor mode not implemented
   csr.dcsr_rd(12)           <= csr.dcsr_ebreaku when (CPU_EXTENSION_RISCV_U = true) else '0'; -- ebreaku: what happens on ebreak in u-mode? (normal trap OR debug-enter)
   csr.dcsr_rd(11)           <= '0'; -- stepie: interrupts are disabled during single-stepping

diff --git a/rtl/core/neorv32_cpu_regfile.vhd b/rtl/core/neorv32_cpu_regfile.vhd
@@ -65,7 +65,7 @@ entity neorv32_cpu_regfile is
     alu_i  : in  std_ulogic_vector(XLEN-1 downto 0); -- ALU result
     mem_i  : in  std_ulogic_vector(XLEN-1 downto 0); -- memory read data
     csr_i  : in  std_ulogic_vector(XLEN-1 downto 0); -- CSR read data
-    pc2_i  : in  std_ulogic_vector(XLEN-1 downto 0); -- next PC
+    npc_i  : in  std_ulogic_vector(XLEN-1 downto 0); -- next PC
     -- data output --
     rs1_o  : out std_ulogic_vector(XLEN-1 downto 0); -- rs1
     rs2_o  : out std_ulogic_vector(XLEN-1 downto 0); -- rs2
@@ -96,13 +96,13 @@ begin
 
   -- Data Write-Back Select -----------------------------------------------------------------
   -- -------------------------------------------------------------------------------------------
-  wb_select: process(ctrl_i, alu_i, mem_i, csr_i, pc2_i)
+  wb_select: process(ctrl_i, alu_i, mem_i, csr_i, npc_i)
   begin
     case ctrl_i.rf_mux is
       when rf_mux_alu_c => rf_wdata <= alu_i; -- ALU result
       when rf_mux_mem_c => rf_wdata <= mem_i; -- memory read data
       when rf_mux_csr_c => rf_wdata <= csr_i; -- CSR read data
-      when rf_mux_npc_c => rf_wdata <= pc2_i; -- next PC (return/link address)
+      when rf_mux_npc_c => rf_wdata <= npc_i; -- next PC (return/link address)
       when others       => rf_wdata <= alu_i; -- don't care
     end case;
   end process wb_select;

diff --git a/rtl/core/neorv32_fifo.vhd b/rtl/core/neorv32_fifo.vhd
@@ -65,13 +65,16 @@ end neorv32_fifo;
 
 architecture neorv32_fifo_rtl of neorv32_fifo is
 
+  -- make sure FIFO depth is a power of two --
+  constant fifo_depth_c : natural := cond_sel_natural_f(is_power_of_two_f(FIFO_DEPTH), FIFO_DEPTH, 2**index_size_f(FIFO_DEPTH));
+
   -- FIFO --
-  type fifo_data_t is array (0 to FIFO_DEPTH-1) of std_ulogic_vector(FIFO_WIDTH-1 downto 0);
+  type fifo_data_t is array (0 to fifo_depth_c-1) of std_ulogic_vector(FIFO_WIDTH-1 downto 0);
   type fifo_t is record
     we    : std_ulogic; -- write enable
     re    : std_ulogic; -- read enable
-    w_pnt : std_ulogic_vector(index_size_f(FIFO_DEPTH) downto 0); -- write pointer
-    r_pnt : std_ulogic_vector(index_size_f(FIFO_DEPTH) downto 0); -- read pointer
+    w_pnt : std_ulogic_vector(index_size_f(fifo_depth_c) downto 0); -- write pointer
+    r_pnt : std_ulogic_vector(index_size_f(fifo_depth_c) downto 0); -- read pointer
     data  : fifo_data_t; -- fifo memory
     buf   : std_ulogic_vector(FIFO_WIDTH-1 downto 0); -- if single-entry FIFO
     match : std_ulogic;
@@ -84,16 +87,10 @@ architecture neorv32_fifo_rtl of neorv32_fifo is
   signal fifo : fifo_t;
 
   -- misc --
-  signal level_diff : std_ulogic_vector(index_size_f(FIFO_DEPTH) downto 0);
+  signal level_diff : std_ulogic_vector(index_size_f(fifo_depth_c) downto 0);
 
 begin
 
-  -- Sanity Checks --------------------------------------------------------------------------
-  -- -------------------------------------------------------------------------------------------
-  assert not (FIFO_DEPTH = 0) report "NEORV32 CONFIG ERROR: FIFO depth has to be > 0." severity error;
-  assert not (is_power_of_two_f(FIFO_DEPTH) = false) report "NEORV32 CONFIG ERROR: FIFO depth has to be a power of two." severity error;
-
-
   -- Access Control -------------------------------------------------------------------------
   -- -------------------------------------------------------------------------------------------
   fifo.re <= re_i when (FIFO_SAFE = false) else (re_i and fifo.avail); -- SAFE = read only if data available
@@ -127,7 +124,7 @@ begin
   -- FIFO Status ----------------------------------------------------------------------------
   -- -------------------------------------------------------------------------------------------
   check_large:
-  if (FIFO_DEPTH > 1) generate
+  if (fifo_depth_c > 1) generate
     fifo.match <= '1' when (fifo.r_pnt(fifo.r_pnt'left-1 downto 0) = fifo.w_pnt(fifo.w_pnt'left-1 downto 0)) else '0';
     fifo.full  <= '1' when (fifo.r_pnt(fifo.r_pnt'left) /= fifo.w_pnt(fifo.w_pnt'left)) and (fifo.match = '1') else '0';
     fifo.empty <= '1' when (fifo.r_pnt(fifo.r_pnt'left)  = fifo.w_pnt(fifo.w_pnt'left)) and (fifo.match = '1') else '0';
@@ -136,7 +133,7 @@ begin
   end generate;
 
   check_small:
-  if (FIFO_DEPTH = 1) generate
+  if (fifo_depth_c = 1) generate
     fifo.match <= '1' when (fifo.r_pnt(0) = fifo.w_pnt(0)) else '0';
     fifo.full  <= not fifo.match;
     fifo.empty <= fifo.match;
@@ -176,7 +173,7 @@ begin
   -- FIFO Memory - Write --------------------------------------------------------------------
   -- -------------------------------------------------------------------------------------------
   fifo_memory: -- real FIFO memory (several entries)
-  if (FIFO_DEPTH > 1) generate
+  if (fifo_depth_c > 1) generate
     sync_read: process(clk_i)
     begin
       if rising_edge(clk_i) then
@@ -189,7 +186,7 @@ begin
   end generate;
 
   fifo_buffer: -- simple register (single entry)
-  if (FIFO_DEPTH = 1) generate
+  if (fifo_depth_c = 1) generate
     sync_read: process(clk_i)
     begin
       if rising_edge(clk_i) then
@@ -208,7 +205,7 @@ begin
   if (FIFO_RSYNC = false) generate
     async_read: process(fifo)
     begin
-      if (FIFO_DEPTH = 1) then
+      if (fifo_depth_c = 1) then
         rdata_o <= fifo.buf;
       else
         rdata_o <= fifo.data(to_integer(unsigned(fifo.r_pnt(fifo.r_pnt'left-1 downto 0))));
@@ -221,7 +218,7 @@ begin
     async_read: process(clk_i)
     begin
       if rising_edge(clk_i) then
-        if (FIFO_DEPTH = 1) then
+        if (fifo_depth_c = 1) then
           rdata_o <= fifo.buf;
         else
           rdata_o <= fifo.data(to_integer(unsigned(fifo.r_pnt(fifo.r_pnt'left-1 downto 0))));

diff --git a/rtl/core/neorv32_package.vhd b/rtl/core/neorv32_package.vhd
@@ -59,7 +59,7 @@ package neorv32_package is
 
   -- Architecture Constants -----------------------------------------------------------------
   -- -------------------------------------------------------------------------------------------
-  constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01090004"; -- hardware version
+  constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01090005"; -- hardware version
   constant archid_c     : natural := 19; -- official RISC-V architecture ID
   constant XLEN         : natural := 32; -- native data path width, do not change!