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🐛 Remove RVC float load/store instructions #771

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merged 3 commits into from Jan 24, 2024
Merged

🐛 Remove RVC float load/store instructions #771

merged 3 commits into from Jan 24, 2024

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stnolting
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Compressed floating point load/store operations are not supported by the Zfinx ISA extension and have to trap.

Bug identified by @mikaelsky in #770.

These ops are not supported for the Zfinx ISA extension
@stnolting stnolting added bug Something isn't working risc-v compliance Modification to comply with official RISC-V specs. HW hardware-related labels Jan 23, 2024
@stnolting stnolting self-assigned this Jan 23, 2024
@stnolting stnolting linked an issue Jan 23, 2024 that may be closed by this pull request
@stnolting stnolting marked this pull request as ready for review January 23, 2024 22:14
@stnolting stnolting merged commit 5281589 into main Jan 24, 2024
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@stnolting stnolting deleted the fix_c_zfinx branch January 24, 2024 07:17
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bug Something isn't working HW hardware-related risc-v compliance Modification to comply with official RISC-V specs.
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Illegal compressed instruction reports 2 traps.
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