🐛 fix atomic write/clear/set accesses of clear-only CSR bits #829
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This is a rework of #821 trying to finally fix #818.
CSR bits that can change at any time and provide clear-only behavior need special handling when performing CSR write/clear/set operations. The modifications from this PR ensure that only the intended bits are touched at all.
Effected CSRs:
mip[.firq]tdata1[.hit]mipis clear-only again - writing ones has no effect at all (reverting the access changes from #821).