鈿狅笍 remove WDT + TRNG interrupts; 馃悰 fix bug in core-complex clocking during sleep #858
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stnolting
added
bug
remove WDT and TRNG interrupts (FIRQs 0 and 15)
- add XCACHE - add XIP-CACHE - remove TRNG & WDT interrupts
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馃悰 Fix Clocking of Core Complex
When the CPU is in sleep mode and clock gating is enabled the I- and D-caches are also halted. This can cause a problems if the clock of the caches gets halted while they are still performing bus operations (e.g. a synchronization flush).
The WDT should not "inform" the software of an impending watchdog timeout, as this could allow the software to reset the watchdog even if the main application is already running incorrectly.
See #844 (comment) by @mikaelsky.
The TRNG interrupt was used to inform software that a certain amount of "entropy" is available. However, this feature seems to be over-engineered.
Note
This PR is part of a series that aims to unify (and simplify) the entire interrupt system of the processor.