⚠️ rework TWI interrupt #860
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The interrupt of the TWI module will now become set whenever the module is in idle state (e.g. after completing an operation).
XIRQ Interrupt
The CPU interrupt of the XIRQ module will now stay high until explicitly acknowledge by writing to the module's
ESCregister.Note
This PR is part of a series that aims to unify (and simplify) the entire interrupt system of the processor.