馃悰 fix DMA fence flag, 鈿狅笍 rework CPU FIRQs #864
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stay high while "done" is set
write accesses are ignored
mip is read-only now
obsolete; just use MIE access
stnolting
added
bug
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馃悰 Fix Bug in DMA's "fence" Control Register Bit
Bit 2 of the control register should be used for this but the hardware was using bit 3.
The standard RISC-V machine interrupt (like the timer interrupt MTI) are level-triggered. With this PR the NEORV32-specific fast interrupt requests (FIRQs) now also follow this standard.
mipCSR is now Read-Onlymipshows all current pending interrupt sources (all interrupt lines that are high). Writing to this register has no effect and is ignored by the hardware. All interrupts keep pending until the interrupt-causing source is cleared (e.g. by reading from a RX FIFO that was signaling "data available").Note
This PR is part of a series that aims to unify (and simplify) the entire interrupt system of the processor.