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fix external debug-halt vs. exception concurrency #882

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merged 3 commits into from Apr 23, 2024
Merged

fix external debug-halt vs. exception concurrency #882

merged 3 commits into from Apr 23, 2024

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stnolting
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@stnolting stnolting commented Apr 23, 2024 •
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Fixing #879.

The CPU can now be halted right after reset before the first instruction is executed. However, the on-chip debugger does not provide the "halt on reset" functionality yet (but that can be emulated by the debugger).

@stnolting stnolting added bug Something isn't working risc-v compliance Modification to comply with official RISC-V specs. HW hardware-related labels Apr 23, 2024
@stnolting stnolting self-assigned this Apr 23, 2024
@stnolting stnolting changed the title fix exteranl debug-halt vs. exception concurrency fix external debug-halt vs. exception concurrency Apr 23, 2024
@stnolting stnolting linked an issue Apr 23, 2024 that may be closed by this pull request
JTAG halt request gets missed if it occures during an illegal instruction #879
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mikaelsky
mikaelsky approved these changes Apr 23, 2024
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Looks good to me. Will see if I can patch up my 1.9.3 core version with this change to do a real-time debug on an FPGA.

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I've tested this by replacing the IMEM by a constant x"00000000" (illegal instruction) and I was able to halt the core at any time (even right after reset 🎉).

So, hopefully, this fixed the "bug".

Thanks again for your help! 👍

@stnolting stnolting marked this pull request as ready for review April 23, 2024 19:41
@stnolting stnolting merged commit 5d45438 into main Apr 23, 2024
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@stnolting stnolting deleted the halt_vs_exception branch April 23, 2024 20:42
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bug Something isn't working HW hardware-related risc-v compliance Modification to comply with official RISC-V specs.
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JTAG halt request gets missed if it occures during an illegal instruction
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