randomization files

.gitignore

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+**/*~

README.md

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 # systemverilog.io
+
+## Introduction
+Welcome to systemverilog.io. You'll find all the code used in https://systemverilog.io here.
+
+General notes:
+
+* The table of contents below specifies which article a directory belongs to.
+* Each directory has a `readme.md` which has instructions to run the examples
+* You'll also find instructions to run an example at the head of the `.sv` file. For example checkout the head of `random-number-generation/prng1.sv`
+
+## Table of Contents
+
+1. `random-number-generation`:  [SystemVerilog Randomization & Random Number Generation](https://systemverilog.io/randomization.html)

random-number-generation/Makefile

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+clean:
+	rm -rf simv* csrc* *.tmp *.vpd *.key log *.h temp *.log .vcs* *.txt DVE* *~ veloce* work transcript

random-number-generation/prng1.sv

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+/*
+ * Article:
+ *  SystemVerilog Randomization & Random Number Generation
+ *
+ * Description:
+ *  Code used in example 1 
+ *
+ * Run instructions:
+ *  This code has been run with Synopsys VCS and with Mentor Graphics Questa Sim.
+ *  General format
+ *  ./run_vcs.sh prng1.sv +define+<example_number> +SEED=<seed>
+ *  ./run_questa.sh prng1.sv +define+<example_number> +SEED=<seed>
+ *
+ *  For example:
+ *  ./run_vcs.sh prng1.sv +define+EX_1_1 +SEED=20
+ *  ./run_questa.sh prng1.sv +define+EX_1_1 +SEED=20
+ *
+ * ARG1 (Required): +define+<example_number> 
+ *  The <example_number> argument corresponds to the example number in
+ *  the article. So, to run example 1.2 you have to pass the command
+ *  line arg +define+EX_1_2
+ * 
+ * ARG2 (Optional): +SEED=<seed>
+ *  This is an optional argument, use it if the example involves using it.
+ *
+ * Commands to run each example:
+ * (use run_questa.sh instead of run_vcs.sh to run with Mentor simulator):
+ * example 1.1: ./run_vcs.sh prng1.sv +define+EX_1_1 
+ * example 1.2: ./run_vcs.sh prng1.sv +define+EX_1_2
+ * example 1.3: ./run_vcs.sh prng1.sv +define+EX_1_3
+ * example 1.4: ./run_vcs.sh prng1.sv +define+EX_1_4
+ * example 1.5A:./run_vcs.sh prng1.sv +define+EX_1_5A +SEED=20
+ * example 1.5B:./run_vcs.sh prng1.sv +define+EX_1_5B +SEED=20
+ */
+program automatic test;
+    class pkt;
+        rand logic [7:0] saddr, daddr;
+        rand logic [3:0] etype;
+        logic [15:0] pkt_size;
+
+        function new();
+            pkt_size = 100; 
+        endfunction: new
+
+        function logic [7:0] get_num();
+            logic [7:0] scope_var;
+
+            `ifdef EX_1_1
+            // Using the class's in-built randomize
+            randomize(pkt_size);
+            // Using SV std lib's scope randomize
+            std::randomize(scope_var);
+            `endif
+
+            `ifdef EX_1_2
+            /* Interchanging the class & scope randomize usage */
+            // Using SV std lib's scope randomize
+            std::randomize(pkt_size);
+            // Using the class's in-built randomize
+            randomize(scope_var);
+            `endif
+
+            `ifdef EX_1_3
+            // Using the class's in-built randomize
+            randomize(pkt_size) with {
+                pkt_size inside {[10:50]};
+            };
+            // Using SV std lib's scope randomize
+            std::randomize(scope_var) with {
+                scope_var inside {10, 20, 30};
+            };
+            `endif
+
+            $display("pkt.get_num: pkt_size %0d scope_var %0d", pkt_size, scope_var);
+        endfunction: get_num
+
+        function void seeding(int seed);
+            logic [7:0] scope_var;
+            $display("seeding: seed is %0d", seed);
+            // Call srandom only if the seed arg is non-zero
+            if (seed != 0)
+                srandom(seed);
+            randomize(pkt_size);
+            std::randomize(scope_var);
+
+            $display("pkt.seeding: pkt_size %0d scope_var %0d", pkt_size, scope_var);
+        endfunction: seeding
+    endclass: pkt
+
+    initial begin
+        pkt p;
+        int unsigned var_a;
+        logic [47:0] var_b;
+        logic [7:0] var_c;
+        integer seed;
+
+        $display("running test");
+        p = new();
+
+        `ifndef EX_1_4
+            `ifndef EX_1_5A `ifndef EX_1_5B
+            // Don't call this piece of code for examples 1.4, 1.5A & 1.5B
+                p.get_num();
+            `endif `endif
+        `elsif EX_1_4
+        for (int i=0; i<5; i++) begin
+            /* Calling randomize() on an object does not randomize 
+             * non-rand variables
+             */
+            p.randomize();
+            $display("p[%0d] -> saddr %d, daddr %d, etype %d, pkt_size %d",
+                i ,p.saddr, p.daddr, p.etype, p.pkt_size);
+        end
+        `endif
+
+        `ifdef EX_1_5A
+        if ($value$plusargs("SEED=%d", seed)) begin
+            $display("SEED entered %0d", seed);
+        end else begin
+            seed = 0;
+        end
+        p.seeding(seed);
+        `endif
+
+        `ifdef EX_1_5B
+        if ($value$plusargs("SEED=%d", seed)) begin
+            $display("SEED entered %0d", seed);
+        end else begin
+            seed = 0;
+        end
+        p.srandom(seed);
+        // Pass seed function arg as 0 so that the seeding function
+        // does not call srandom.
+        p.seeding(0);
+        `endif
+
+        `ifdef EX_1_6
+        for (int i=0; i<5; i++) begin
+            p.randomize();
+            $display("p[%0d] -> saddr %d, daddr %d, etype %d",
+                i ,p.saddr, p.daddr, p.etype);
+        end
+        std::randomize(var_a, var_c);
+        $display("var_a 0x%x var_c 0x%x", var_a, var_c);
+        `endif
+
+    end
+endprogram

random-number-generation/prng2.sv

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+/*
+ * Article:
+ *  Deep Dive: SystemVerilog Randomization & Random Number Generation
+ *
+ * Description:
+ *  Code used in example 2 
+ *
+ * Run instructions:
+ * (use run_questa.sh instead of run_vcs.sh to run with Mentor simulator):
+ * example 2.1: ./run_vcs.sh prng2.sv +define+EX_2_1
+ * example 2.2: ./run_vcs.sh prng2.sv +define+EX_2_2 +SEED=20
+ */
+program automatic test;
+    initial begin
+        int unsigned var_a, var_d;
+        logic [63:0] var_b;
+        logic [7:0] var_c;
+        int seed;
+
+        `ifdef EX_2_1
+        var_a = $urandom();
+        var_c = $urandom_range(10, 20);
+        $display("var_a 0x%x var_c 0x%x", var_a, var_c);
+
+        var_b = $urandom();
+        $display("Using $urandom() to randomize 64bit var, var_b = 0x%x", var_b);
+
+        var_b = {$urandom(), $urandom()};
+        $display("Using shifted $urandom(), var_b = 0x%x", var_b);
+
+        std::randomize(var_b);
+        $display("std::randomize(var_b) = 0x%x", var_b);
+        `endif
+
+        `ifdef EX_2_2
+        if ($value$plusargs("SEED=%d", seed)) begin
+            $display("SEED entered %0d", seed);
+        end else begin
+            seed = 0;
+        end
+        if (seed != 0) begin
+            var_a = $urandom(seed);
+        end else begin
+            var_a = $urandom();
+        end
+        var_b = $urandom();
+        var_d = $urandom_range(10, 2000);
+        $display("var_a 0x%x var_b 0x%x var_d 0x%x", var_a, var_b, var_d);
+        `endif
+    end
+endprogram

random-number-generation/prng3.sv

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+/*
+ * Article:
+ *  SystemVerilog Randomization & Random Number Generation
+ *
+ * Description:
+ *  Code used in example 3 
+ *
+ * Run instructions:
+ * (use run_questa.sh instead of run_vcs.sh to run with Mentor simulator):
+ * example 3.1: ./run_vcs.sh prng3.sv +define+EX_3_1
+ * example 3.2: ./run_vcs.sh prng3.sv +define+EX_3_2
+ * example 3.3: ./run_vcs.sh prng3.sv +define+EX_3_3
+ * example 3.4: ./run_vcs.sh prng3.sv +define+EX_3_4
+ */
+program automatic test;
+    initial begin
+        int var_a, var_b, var_c, seed, seed1, seed2, seed3;
+        string str, str2;
+
+        `ifdef EX_3_1
+        for (int i=0; i<5; i++) begin
+            var_a = $random;
+            var_b = $dist_poisson(seed, 100);
+            $display("%0d -> var_a %d var_b %d", i, var_a, var_b);
+        end
+        `endif
+
+        `ifdef EX_3_2
+        // Using 3 different seed vars for a specific reason. Read the seeding section
+        // of the article to find out why.
+        seed1 = 10;
+        seed2 = 10;
+        seed3 = 10;
+        for (int i=0; i<5; i++) begin
+            var_a = {$random(seed1)}; var_b = $random(seed2)%50; var_c = {$random(seed3)}%50;
+            $display("$random %0d -> var_a %d var_b %3d var_c %3d", i, var_a, var_b, var_c);
+        end
+        `endif
+
+        `ifdef EX_3_3
+        seed = 10;
+        for (int i=0; i<5; i++) begin
+            // "seed" is an INOUT var, calling $random, $dist_normal, etc
+            // take the seed as an input and does 2 things on return -
+            // 1. returns a 32-bit random number, which is stored in var_a
+            // 2. changes the value of "seed" so that the next call to random
+            // .. uses this "new" seed set by the previous call to generate the
+            // .. next random number. 
+            // This is how $random guarantees that for a given starting seed,
+            // the sequence of random numbers generated is always the same.
+            var_a = $random(seed);
+            $display("Loop #%0d. var_a %d next-seed %0d", i, var_a, seed);
+        end
+        `endif
+
+        `ifdef EX_3_4
+        if ($value$plusargs("SEED=%d", seed)) begin
+            $display("SEED entered %0d", seed);
+        end else begin
+            seed = 20;
+        end
+        seed1 = seed;
+        seed2 = seed;
+        for (int i=0; i<5; i++) begin
+            var_a = $random(seed1); var_b = $random(seed2);
+            $display("$random %0d -> var_a %d var_b %d", i, var_a, var_b);
+        end
+        `endif
+    end
+endprogram

random-number-generation/readme.md

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+Article:
+ SystemVerilog Randomization & Random Number Generation
+
+Description:
+ Commands to run examples 
+
+Run instructions:
+ This code has been run with Synopsys VCS and with Mentor Graphics Questa Sim.
+ General format
+ ./run_vcs.sh prng1.sv +define+<example_number> +SEED=<seed>
+ ./run_questa.sh prng1.sv +define+<example_number> +SEED=<seed>
+
+ For example:
+ ./run_vcs.sh prng1.sv +define+EX_1_1 +SEED=20
+ ./run_questa.sh prng1.sv +define+EX_1_1 +SEED=20
+
+ARG1 (Required): +define+<example_number> 
+ The <example_number> argument corresponds to the example number in
+ the article. So, to run example 1.2 you have to pass the command
+ line arg +define+EX_1_2
+
+ARG2 (Optional): +SEED=<seed>
+ This is an optional argument, use it if the example involves using it.
+
+Commands to run example 1:
+(use run_questa.sh instead of run_vcs.sh to run with Mentor simulator):
+example 1.1: ./run_vcs.sh prng1.sv +define+EX_1_1 
+example 1.2: ./run_vcs.sh prng1.sv +define+EX_1_2
+example 1.3: ./run_vcs.sh prng1.sv +define+EX_1_3
+example 1.4: ./run_vcs.sh prng1.sv +define+EX_1_4
+example 1.5A:./run_vcs.sh prng1.sv +define+EX_1_5A +SEED=20
+example 1.5B:./run_vcs.sh prng1.sv +define+EX_1_5B +SEED=20
+
+Commands to run example 2:
+example 2.1: ./run_vcs.sh prng2.sv +define+EX_2_1
+example 2.2: ./run_vcs.sh prng2.sv +define+EX_2_2 +SEED=20
+
+Commands to run example 3:
+example 3.1: ./run_vcs.sh prng3.sv +define+EX_3_1
+example 3.2: ./run_vcs.sh prng3.sv +define+EX_3_2
+example 3.3: ./run_vcs.sh prng3.sv +define+EX_3_3
+example 3.4: ./run_vcs.sh prng3.sv +define+EX_3_4

random-number-generation/run_questa.sh

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+#!/bin/sh
+
+# compile code
+vlog $1 $2
+# check if compile passed by checking exit code of previous command
+if [ "$?" = "0" ]; then
+    # run simulation
+    vsim -c test -sv_seed 10 $3 -do "run -all"
+else
+    echo "Compile Failed"
+fi
+

random-number-generation/run_vcs.sh

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+#!/bin/sh
+
+# compile code
+vcs -sverilog -l comp.log -timescale=1ns/1ps -full64 $1 $2;
+# check if compile passed by checking exit code of previous command
+if [ "$?" = "0" ]; then
+    # run simulation
+    ./simv +ntb_random_seed=10 +vcs+lic+wait $3
+else
+    echo "Compile Failed"
+fi